Ex Parte Conti et al

Patent Trial and Appeal Board

Mar 25, 2014

10961755 (P.T.A.B. Mar. 25, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte GREGORY REMY PHILIPPE CONTI
and JEROME LAURENT AZEMA
____________

Appeal 2011-009909
Application 10/961,755
Technology Center 2100
____________

Before JOSEPH F. RUGGIERO, MAHSHID D. SAADAT,
and CARLA M. KRIVAK, Administrative Patent Judges.

SAADAT, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 32-62.1 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 Claims 1-31 have been cancelled.
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STATEMENT OF THE CASE
Introduction
Appellants’ invention relates to secure mode operation of system-on-
a-chip (SoC) devices for ensuring integrity of a secure mode entry sequence
(Spec. ¶¶ [0003], [0008]). Claim 32, which is representative of the
invention, reads as follows:
32. A method of monitoring a computing system, comprising
the steps of:
monitoring a processing device within the computing
system;
determining whether a last instruction operated upon by
the processing device was an expected instruction;
if the last instruction was not an expected instruction,
generating a signal indicating a security violation;
if the last instruction was an expected instruction,
determining whether the last instruction was executed.
The Examiner’s Rejections
Claims 32-40, 42-53, and 55-62 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Dahan (US 2003/0140205 A1). (See
Ans. 3-12).
Claims 41 and 54 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Dahan and McGregor (John P. McGregor et al., A
Processor Architecture Defense against Buffer Overflow Attacks, PROC.
IEEE INT’L CONF. ON INFO. TECH.: RES. EDUC. 243-50 (2003)). (See Ans.
13-14).
Appellants’ Contentions
With respect to independent claims 32 and 45, Appellants present the
following contentions:
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1. While Dahan checks for correctness of an “ACTIVATION
SEQUENCE,” no evidence was provided by the Examiner that it is “a last
instruction” operated upon by the processor (App. Br. 5). Appellants further
assert the Branch/ESA[SR] instruction in table 2 of Dahan is continued by
other instructions the processor follows and therefore, cannot be the last
instruction (App. Br. 6).
2. The activation sequence discussed in Dahan’s paragraphs 83,
84, and 86 is not monitored, and therefore, signal 542 is generated after a
secure operation is executed, rather than in response to a violation of the
activation sequence (App. Br. 7).
3. The Examiner did not identify any teaching in Dahan,
especially in tables 1 and 3, to show whether the last instruction was an
expected instruction or whether it was actually executed (id.).
4. The proposed modification to Dahan that it would have been
obvious that “an instruction abort during activation sequence and executing
secure mode operations would generate a security violation” is not supported
by evidence or articulated reasoning (App. Br. 8 (emphasis omitted)).
With respect to claims 33 and 46, Appellants rely on the same reasons
argued for claims 32 and 45 and further contend the cited portions of Dahan
in Figure 5, paragraphs 83 and 86, or tables 1 and 3, do not teach issuing a
security violation signal if the last instruction was not executed or otherwise,
determining an internal exception or abort (App. Br. 11, 14).
Regarding claims 34 and 47, in addition to the same reasons stated for
claims 33 and 46, Appellants similarly argue the Examiner has not provided
evidence it would have been obvious to generate a security violation signal
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or make the recited determination with respect to the last instruction (App.
Br. 11-12, 14-15).
With respect to claims 35 and 48, Appellants rely on the same reasons
argued for claims 34 and 47 and further contend the cited portions of Dahan
in table 1 include no discussion of “branch phantoms” or “decode errors”
and whether they are associated with a “last instruction” (App. Br. 12, 15).
With respect to the remaining claims, Appellants argue their
patentability based on their dependency from their base claims, or in case of
claims 41 and 54, based on the failure of McGregor to disclose the features
missing from Dahan (App. Br. 12-18). Therefore, the remaining claims
stand or fall with their corresponding base claims.
Issue on Appeal
Appellants’ contentions present us with the following issue:
Has the Examiner erred in rejecting the claims as being obvious over
Dahan because the proposed modifications do not teach or suggest all the
claim features?

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner has erred. We disagree with Appellants’
conclusions. We adopt as our own the findings and reasons set forth by the
Examiner in the action from which this appeal is taken and the reasons set
forth by the Examiner in the Examiner’s Answer in response to Appellants’
Appeal Brief (see Ans. 14-21). However, we highlight and address specific
findings and arguments for emphasis as follows.
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Claims 32 and 45
With respect to the above contention 1, the Examiner responds by
relying on the broadest reasonable interpretation of “last instruction” as “the
last instruction executed by the processor at any given time during
execution” (Ans. 15-16). The Examiner further points to paragraph 83 and
table 1 of Dahan for teaching various sequence entry conditions as well as
those that cause activation sequence violations which cause a global reset,
thus making the violating instruction the last instruction (Ans. 16). We
agree with the Examiner’s claim interpretation and findings.
Regarding the above contention 2, we also agree with the Examiner
that elements 524 and 528 in Figure 5 of Dahan both generate security
violations when unexpected instructions fetched outside the secure
ROM/RAM are detected (Ans. 17 (citing Dahan ¶ [0086])).
Regarding the above contention 3, the Examiner did in fact pointed to
paragraph 96 of Dahan and explained the non-operational (NOP) instruction
as the last instruction that did not cause any security violation would have
been recognized by one of ordinary skill in the art as the expected instruction
to be executed and completed by the processor pipeline (Ans. 18 (citing
Dahan table 2; ¶ [0096])).
Lastly, we agree with the Examiner’s findings and conclusion with
respect to the above contention 4. Specifically, as pointed out by the
Examiner, one of ordinary skill in the art would have equated a failing of
any entry conditions of table 1 with generating a security violation (id.). The
Examiner further correctly characterized the signals listed in table 3 as
signals necessary for a secure environment, whose monitoring would lead to
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detecting security violations (Ans. 18-19 (citing Dahan table 3; ¶¶ [0104],
[0110])).
Claims 33-35 and 46-48
In response to each of the arguments raised by Appellants, the
Examiner presents detailed findings and responses (Ans. 19-21). We agree
with these findings and conclusions and adopt them as our own. For
example, the Examiner properly found item 4 in table 1 of Dahan shows a
security violation resulting in instruction/data aborts (Ans. 19-20).
Similarly, the Examiner correctly pointed to item 8 in table 1 as the situation
in which the processor did not experience an exception or instruction/data
aborts (Ans. 21). Finally, the Examiner properly found the claimed
detecting a decode error resulting in a security violation is met by the
security violation generated when a Thumb/Java instruction is fetched by the
processor in Dahan (id.).

CONCLUSION
On the record before us, we conclude, because the proposed
modifications to Dahan teach or suggest all the disputed claim limitations,
the Examiner did not err in rejecting the claims as being obvious over Dahan
or Dahan in view of McGregor.

DECISION
The decision of the Examiner rejecting claims 32-62 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

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AFFIRMED

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