Ex Parte Conner

Board of Patent Appeals and Interferences

Sep 14, 2010

11252341 (B.P.A.I. Sep. 14, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte BRYAN CONNER
____________

Appeal 2009-008365
Application 11/252,341
Technology Center 2100
____________

Before KENNETH W. HAIRSTON, ST. JOHN COURTENAY III, and
ELENI MANTIS MERCADER, Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL1

STATEMENT OF THE CASE
Appellant seeks our review under 35 U.S.C. § 134 of the Examiner’s
final decision rejecting claims 1-17. We have jurisdiction over the appeal
under 35 U.S.C. § 6(b).

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

Appeal No. 2009-008365
Application 11/252,341

2
We Reverse.
Invention
Appellant’s invention on appeal relates generally to software, systems
and methods for dynamic priority conflict resolution in multiprocessor
computer systems. More particularly, Appellant’s invention is directed to
conflict resolution in multiprocessor computer systems having shared
memory with equal priority values. (App. Br. 1).
Claims 1 and 13 are illustrative:
1. A computer system including a plurality of
processing elements requiring access to a shared resource, said
computer system comprising:
a priority conflict resolution circuit comparator for dynamically
resolving a priority tie among a plurality of processing elements
simultaneously requesting access to said shared resource, the
priority tie resulting from more than one of said plurality of
processing elements to be of a common highest priority, said
priority conflict resolution circuit comparator including an
initial predetermined differing priority tie precedence assigned
corresponding to each of said plurality of said processing
elements wherein upon a selected one of said plurality of
processing elements being afforded access to said shared
resource based upon said initial priority tie precedence thereof
being a highest priority of said plurality of processing elements
and wherein an identity of the selected one of said plurality of
said processors is stored so as upon a subsequent priority tie of
said plurality of processing elements the selected one of said
plurality of said processors is prevented from being selected
again until each remaining processing element of the plurality
of processing elements is selected.
13. A computer system including a plurality of
processing elements and a shared resource, said computer
system comprising:
Appeal No. 2009-008365
Application 11/252,341

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a dynamic conflict resolution circuit for controlling
access to said shared resource among said processing elements,
said dynamic conflict resolution circuit including a conflict
priority scheme for resolving two or more simultaneous
processing element requests to access said memory resources
wherein, responsive to request activity being isolated to a single
active port, said conflict priority scheme maintaining current
processing element priority level of each processor element for
at least one processing cycle.
Appellant appeals the following rejections:
1. Claims 1-5, 8-11, 13, 15, and 16 under 35 U.S.C. § 102(a) as anticipated
by Deneroff (US 2005/0053057 A1, Mar. 10, 2005).
2. Claim 6 is rejected under 35 U.S.C. § 103(a) as unpatentable over
Deneroff.
3. Claims 7, 12, 14, and 17 under 35 U.S.C. § 103(a) as unpatentable over
Deneroff and Epstein (US 5,016,162, Mar. 14, 1991).

ISSUES
Based upon our review of the administrative record, we have
determined that the following issues are dispositive in this appeal:
(1) Under §102, did the Examiner err in determining that Deneroff
discloses storing an identity of a selected processor so as upon a subsequent
priority tie of said plurality of processing elements the selected one of said
plurality of said processors is prevented from being selected again until each
remaining processing element of the plurality of processing elements is
selected? (See claims 1 and 8).
Appeal No. 2009-008365
Application 11/252,341

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(2) Did the Examiner fail to establish a proper prima facie case of
anticipation by not addressing each claimed element in the rejection of
independent claims 13 and 16?

FACTUAL FINDING
1. Deneroff discloses that the arbiter priority module always selects
the oldest age of the output queue (OQ). In the case of a tie, the priority
block will select the winner according to the round-robin pointer. The
pointer advances every grant cycle, regardless of the grant results. (Para.
[0257]).

ANALYSIS
ISSUE (1)

Independent claims 1 and 8

Appellant argues that the Examiner has mischaracterized claims 1 and
8 as merely reciting a round-robin pointer. (App. Br. 10). Appellant contends
that “Deneroff does not describe retaining a history of the results of the
[priority] tie.” (App. Br. 11). Thus, Appellant contends that “Deneroff fails
to describe what happens when ‘a subsequent priority tie of said plurality of
processing elements’ occurs. Note that after the initial winner is chosen and
the round robin pointer of Deneroff is determining the next winner, the same
set of said plurality of processing elements is not experiencing a tie. Thus
claims 1 and 8 do not read on Deneroff.” (App. Br. 12; see also claims 1 and
8).

Appeal No. 2009-008365
Application 11/252,341

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The Examiner disagrees. The Examiner contends that Deneroff
discloses a round-robin selection scheme. (Ans. 4, 6). According to the
Examiner, Deneroff discloses “the pointer is stored to indicate which . . .”
[processor] “is to be granted” [and] “the fact that the value of the pointer
advances to the next processor after the grant does not alleviate the fact that
the pointer initially stores the value of the processor granted.” (Ans. 6, last
paragraph).
Based upon our review of the record, we find the evidence before us
supports the Appellant’s position.
At the outset, we observe that the Examiner relies upon an extrinsic
dictionary definition of “round-robin” in interpreting the teachings of
Deneroff (Ans. 6, ¶ 3; see also FF 1). The term “round-robin” does not
appear in the claimed invention on appeal.
Deneroff’s discloses a priority block that selects the winner according
to a round-robin pointer in the case of a priority tie. (FF 1). We agree with
Appellant that Deneroff’s disclosure of round-robin resolution of priority
ties does not mean that Deneroff describes retaining a history of the results
of a priority tie (i.e., storing the identity of the selected one) such that the
selected processor is prevented from being selected again upon a subsequent
priority tie until each remaining processing element of the plurality of
processing elements is selected, within the meaning of independent claims 1
and 8. (App. Br. 11).
We also observe that the Examiner’s anticipation rejection of claims 1
and 8 relies principally on Deneroff’s Figures 3 and 8, and paragraph 0257.
(Ans. 3-4). However, paragraph 0257 describes Figure 15, not Figure 3 nor
Figure 8.
Appeal No. 2009-008365
Application 11/252,341

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For these reasons, we do not find, nor has the Examiner established,
that the identity of the selected one of the processors is stored (i.e., a history
is retained) so as upon a subsequent priority tie of said plurality of
processing elements the selected one of said plurality of said processors is
prevented from being selected again until each remaining processing
element of the plurality of processing elements is selected, within the
meaning of independent claims 1 and 8.
Accordingly, we reverse the Examiner’s anticipation rejection of
independent claims 1 and 8, as well as the Examiner’s rejections of
associated dependent claims 2-7 and 9-12.2

ISSUE (2)
Independent claims 13 and 16
We decide the question whether the Examiner failed to establish a
proper prima facie case of anticipation by not addressing each claimed
element in the rejection of independent claims 13 and 16 over Deneroff.
Regarding this issue, we agree with the position articulated by the
Appellant on pages 8-9 of the Brief. In particular, we observe that the
Examiner has only attempted to map the elements of claim 1 to Deneroff.
(Ans. 3-4). Thus, the Examiner cannot rely on the rejection of claim 1 alone
to set forth a prima facie case of anticipation for independent claims 13 and
16, because claims 13 and 16 recite additional features not recited in claim 1.

2 Dependent claims 6, 7 and 12 are rejected under § 103. We do not find,
nor has the Examiner established, that Epstein (see claims 7 and 12) cures
the deficiencies of Deneroff discussed supra.
Appeal No. 2009-008365
Application 11/252,341

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The Examiner failed to address the following additional features, as
described by Appellant:
Claim 13 and claim 16, while being directed to the
same invention, are distinct from claims 1 and 8. Claim
13 is directed to a system having a dynamic conflict
resolution circuit that resolves conflicting request activity
directed toward a shared resource that is isolated to a
single active port. Claim 16 is directed to a
corresponding method for conflict resolution when
request activity for a shared resource is isolated to a
single active port. Rather than address these features, the
Examiner combines them with the minimal analysis
presented for claim 1.

(App. Br. 8).
On this record, we find the Examiner erred in rejecting independent
claims 13 and 16 as being anticipated by Deneroff. Accordingly, we reverse
the Examiner’s § 102 rejection of claims 13 and 16, as well as the associated
rejections of dependent claims 14, 15 and 17.3

3 Dependent claims 14 and 17 are rejected under § 103. We do not find nor
has the Examiner established, that Epstein cures the deficiencies of Deneroff
discussed supra.
Appeal No. 2009-008365
Application 11/252,341

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DECISION
We reverse the Examiner’s § 102 and § 103 rejections.

ORDER
REVERSED

pgc

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