Ex Parte Colglazier

Patent Trial and Appeal Board

Jun 16, 2017

13672896 (P.T.A.B. Jun. 16, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
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P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/672,896 11/09/2012 Daniel J. Colglazier RPS920120073US1 (157) 8397
50594 7590
CRGO LAW
STEVEN M. GREENBERG
7900 Glades Road
SUITE 520
BOCA RATON, EL 33487
06/20/2017 EXAMINER
AHMED, ZUBAIR
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
06/20/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@crgolaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte INTERNATIONAL BUSINESS MACHINES CORP.1
Appeal 2017-001149
Application 13/672,896
Technology Center 2100
Before BRADLEY W. BAUMEISTER, JOHN F. HORVATH, and
MICHAEL J. ENGLE, Administrative Patent Judges.
BAUMEISTER, Administrative Patent Judge.
DECISION ON REQUEST FOR REHEARING
Pursuant to 37 C.F.R. § 41.52, Appellant requests rehearing of our
March 29, 2017, Decision on Appeal (“Decision”). See Request for
Rehearing filed May 30, 2017 (“Request”). In that Decision, we affirmed
the Examiner’s rejection of claims 6—15 under 35 U.S.C. § 103(a) as obvious
over Jaleel (US 2012/0159073 Al; published June 21, 2012) and various
combinations of five additional prior-art references. Dec. 3—9.
We grant Appellant’s Request for Rehearing to the extent that we
reconsider the reasoning of our Decision, as further discussed below, but we
deny Appellant’s Request to modify our ultimate decision affirming the
Examiner’s rejections of claims 6—15. Pursuant to our discretionary
1 Daniel J. Colglazier is the named inventor.
Appeal 2017-001149
Application 13/672,896
authority under 37 C.F.R. § 41.50(b), we designate each of the rejections of
claims 6—8 and 11—13 as constituting new grounds.
STATEMENT OF THE INVENTION
Appellant describes the present invention as follows:
Embodiments of the present invention provide a method,
system and computer program product for enhanced cache
coordination in a multi-level cache. In an embodiment of the
invention, a method for enhanced cache coordination in a multi­
level cache is provided. The method includes receiving a
processor memory request to access data in a multi-level cache
and servicing the processor memory request with data in either
an LI cache or an L2 cache of the multi-level cache. The method
additionally includes marking a cache line in the LI cache and
also a corresponding cache line in the L2 cache as most recently
used responsive to determining that the processor memory
request is serviced from the cache line in the LI cache and that
the cache line in the LI cache is not currently marked most
recently used.
Abstract.
INDEPENDENT CLAIMS 6 AND 11
Independent claim 6, reproduced below with the disputed limitation
emphasized, is illustrative of the appealed subject matter that was argued in
relation to claims 6 and 11 (Request 2-4):
6. A data processing system configured for enhanced cache
coordination in a multi-level cache, the system comprising:
a processor coupled to main memory over a bus;
a multi-level cache accessible to the processor and
comprising an LI cache and an L2 cache;
a cache controller managing access to the multi-level
cache; and,
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Application 13/672,896
an enhanced cache coordination module coupled to the
cache controller and comprising program code enabled to mark
a cache line in the LI cache and also a corresponding cache line
in the L2 cache as most recently used responsive to determining
that the processor memory request is serviced by the cache
controller from the cache line in the LI cache and that the cache
line in the LI cache is not currently marked most recently used.
Findings and Contentions
We stated in our Decision that “[w]e disagree with Appellant’s
contention that the Examiner’s conclusion regarding Jaleel inherently
teaching marking a cache line as MRU upon determining the cache line is
not currently marked as MRU is only conclusory or constitutes mere
conjecture absent factual support.” Decision 5. The Panel then went on to
explain that Jaleel not only supports the Examiner’s finding of inherency,
Jaleel also teaches this feature expressly: “Jaleel states that ‘the LI cache
can issue TLHs [i.e., Temporal Learning Hints] for non-[most recently used
(MRU)] lines.’” Decision 6 (quoting Jaleel 144).
Appellant reasserts on Rehearing that the combination of Jaleel and
Azevedo lacks a teaching of
marking of a cache line in the LI cache and also a corresponding
cache line in the L2 cache as most recently used in response to a
determination that the processor memory request is serviced
from the cache line in the LI cache and also that the cache line
in the LI cache is not currently marked most recently used.
Request 3. More specifically, Appellant argues that
as set forth in paragraph [0043] of Jaleel, a “temporal locality hint”
(TLH) is sent to the lowest level cache (LLC) for every LI cache
hit. And, in response to an LI cache hit, the line is moved to the
MRU position in the LI cache. Likewise, in the LLC, the line is
promoted to MRU. But nothing in paragraph f00431 referred to a
determination that the line in LI is NOT currently marked MRU.
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Application 13/672,896
Request 3^4. In Appellant’s view,
determining to issue a “hint” for a line that is not MRU is not the
same as updating a cache ONLY when the requested line is not
marked MRU. To wit, the term “ONLY” is the source of the
clearly erroneous error as nothing in the cited passage of Jaleel—
namely paragraph [0044]—references exclusivity.
Request 4.
Analysis
Paragraphs 41—43 of Jaleel describe the fundamental protocol for
using temporal locality hints. Appellant is correct that paragraphs 41—43 of
Jaleel teach sending TLHs for every LI hit, including cached LI lines
marked as MRU. However, paragraph 44 of Jaleel explains advantages and
drawbacks of the fundamental TLH protocol and then sets forth two
alternatives for further improving upon that TLH protocol:
TLHs can significantly reduce the number of inclusion
victims because they keep the LLC replacement state up-to-date
with the core caches. However, the downside is that they send a
request to the LLC for every hit in the core caches.
Optimizations may be made by filtering the number of TLHs sent
from the core caches to the LLC. For example, in a multilevel
hierarchy, the second level cache can issue TLHs instead of the
first level cache. Alternatively, the LI cache can issue TLHs for
non-MRU lines.
Jaleel 144 (emphasis added).
Restated, paragraph 44 explains that in order to avoid updating the L2
cache for every hit in the LI cache (e.g., including when the LI hit is for the
most recently used line), the TLH protocol can be optimized by marking the
L2 cache line, as well as the LI cache line, as most recently used only when
the serviced LI cache line is not marked as most recently used.
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Application 13/672,896
We therefore affirm the Examiner’s obviousness rejections based
upon Jaleel’s alternate TLH protocol, as set forth in paragraph 44. Because
our rationale for affirming the Examiner’s rejections of claims 6—8 and 11—
13 constitutes a different thrust from the Examiner’s rationale, which was
that the fundamental TLH protocol inherently teaches the disputed
limitation, we designate each of the rejections of claims 6—8 and 11—13 as
constituting a new ground pursuant to our discretionary authority under
37 C.F.R. § 41.50(b).
INDEPENDENT CLAIM 9
Appellant separately requests the Board reconsider its affirmance of
the rejection of independent claim 9 (Request 4—5), which claim is
reproduced below with the disputed language emphasized:
9. A data processing system configured for enhanced cache
coordination in a multi-level cache, the system comprising:
a processor coupled to main memory over a bus;
a multi-level cache accessible to the processor and
comprising an LI cache and an L2 cache;
a cache controller managing access to the multi-level
cache; and,
an enhanced cache coordination module coupled to the
cache controller and comprising program code enabled to replace
an existing cache line in the LI cache with a cache line from the
L2 cache, and to send an address of the replaced cache line to the
L2 cache and to mark a corresponding cache line in the L2 cache
as least recently used responsive to determining that the replaced
cache line in the LI cache does not exist in any other LI cache
of the multi-level cache.
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Findings and Contentions
The Examiner rejected claim 9 as obvious over a combination of five
references including Walker (US 2013/0311724 Al; published
Nov. 21, 2013). Non-Final Action 13—16 (mailed Nov. 12, 2015). In so
doing, the Examiner found Walker teaches that “responsive to determining that
the replaced cache line in the LI cache does not exist in any other LI cache of
the multilevel cache[s]” (claim 9), “the L2 cache replaces the cache line with a
new cache line.” Id. at 16 (citing Walker 127).
Appellant initially argued on appeal that Walker does not provide
such teaching. App. Br. 15—16. According to Appellant,
Walker [instead] provides for the replacement of a cache line
with a new cache line in response to a determination of whether
or not a cache line is present in only one of the higher level
caches. This teaching stands in stark contrast to Appellants’
plain claim language requirement of a response to a
determination that the replaced cache line in the LI cache does
not exist in ANY other LI cache of the multi-level cache—not
merely in just one of the ^higher level caches*.
Id. at 16.
The Examiner addressed this contention by further explaining
Walker states referring to Figure 3 “step 306 determines if the
cache line is present in any of the higher level, LI, caches. If the
cache line is not present in any of the higher level LI caches, (the
“NO” path of method 300), L2 cache replaces the cache line with
a new cache line”, para 0027. Further, “when a cache line is
evicted from LI cache, [that evicted line] is written back to the
next level in the cache hierarchy, i.e., L2”, para 0012. . . .
[I]n step 304 [of Walker’s Figure 3], a determination is
made if the cache line is present in one of the higher level caches.
The NO path in step 306 is the result of the determination that
none of the higher level LI caches has the cache line.
Ans. 6—7 (emphases added).
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Subsequently, Appellant seemingly shifted arguments in the Reply
Brief. Instead of arguing that Walker only checks one of the LI caches
rather than all of the LI caches, as was argued in the Appeal Brief,
Appellant argued in the Reply Brief that “Walker only teaches a
determination if a cache line is present in any ^higher level caches*—not *any
other LI cache*.” Reply Br. 7.
In our Decision, we focused primarily on Appellant’s initial argument,
which was presented in the Appeal Brief. See Frye, 94 USPQ2d at 1075 (“If
an appellant fails to present arguments on a particular issue — or, more
broadly, on a particular rejection —the Board will not, as a general matter,
unilaterally review those uncontested aspects of the rejection”); see also
37 C.F.R. § 41.41(b)(2) (“Any argument raised in the reply brief [that] was
not raised in the appeal brief, or is not responsive to an argument raised in
the examiner's answer, including any designated new ground of rejection,
will not be considered by the Board for purposes of the present appeal,
unless good cause is shown”). However, in addressing Appellant’s initial
argument in the Appeal Brief, we also addressed the argument Appellant
raised in the Reply Brief.
More specifically, we cited the combination of Walker’s Abstract and
paragraph 27 in agreeing with “the Examiner’s finding that Walker
determines if the requested cache line is present in any of the higher level
caches of the multi-level cache and replaces the cache line only when the
cache line is not present in any of the LI caches.” Decision 8 (emphases
added).
On Rehearing, Appellant now argues that “Walker only teaches a
determination if a cache line is present in any *higher level caches*—not
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Application 13/672,896
*any other LI cache*.” Request 4—5. Appellant further urges that “[t]he
Board’s findings [regarding Walker’s teachings] seem to simply ignore the
observation by Appellants that step 306 of Walker only teaches a
determination if a cache line is present in any *higher level caches*—not
*any other LI cache*.” Id. at 5.
Analysis
We understand Appellant to be arguing that some distinction exists
between “higher level caches” and “LI caches.” We agree that a distinction
exists to the extent that an LI cache is a particular type of a higher level
cache. While “higher level caches” include all caches of a multi-level cache
above a reference point (e.g., above the lowest level cache), the LI cache(s)
more specifically are the highest level cache(s) of the multi-level caches.
However, this distinction is irrelevant because the Decision cites
passages of Walker that clearly indicate that Walker discloses the disputed
language of claim 9. More specifically, we understand claim 9 to require,
inter alia, inspecting all of the LI caches of the multi-level cache system to
determine whether a requested cache line exists in any of the LI caches, and
if the requested cache line does not exist in any of the LI caches, replacing a
cache line of one of the LI caches with the requested cache line, which has
been retrieved from the L2 cache. And this is exactly what Walker teaches:
A cache system includes [a] plurality of first caches at a first
level of a cache hierarchy and a second cache at a second level
of the cache hierarchy which is lower than the first level of cache
hierarchy coupled to each of the plurality of first caches. The
second cache enforces a cache line replacement policy in which
the second cache selects a cache line for replacement based in
part on whether the cache line is present in any of the plurality
of first caches and in part on another factor.
Walker Abstract (emphases added).
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Walker also states in relation to the disputed step 306, “if the cache
line is present in any of the higher level, LI, caches then method 300
proceeds to 308, else method 300 proceeds to 310 and the L2 cache replaces
the cache line with a new cache line.” Walker 127 (emphasis added). We
expressly quoted this teaching of Walker in our Decision. See Decision 8.
For these reasons, we are unpersuaded that the Board has
misapprehended or overlooked Appellant’s arguments regarding claims 7, 9,
10, 12, 14, and 15 as presented in either the Appeal Brief or the Reply Brief.
DECISION
Appellant’s Request for Rehearing is granted to the extent that we
reconsider the reasoning of our Decision in relation to Jaleel, but Appellant’s
Request to modify our ultimate decision affirming the Examiner’s rejections
of claims 6—15 is DENIED.
Because we affirm the rejections of claims 6—8 and 11—13 based upon
Jaleel’s alternate TLH protocol, as set forth in paragraph 44, and because our
rationale for affirming the rejections constitutes a different thrust from the
Examiner’s rationale of the fundamental TLH protocol inherently teaching
the disputed limitation, we designate the rejections of these claims as
constituting a new ground pursuant to our discretionary authority under
37 C.F.R. § 41.50(b). Rule 41.50(b) provides that “[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review.” Rule 41.50(b) also provides the following:
When the Board enters such a non-final decision, the appellant,
within two months from the date of the decision, must exercise
one of the following two options with respect to the new ground
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Application 13/672,896
of rejection to avoid termination of the appeal as to the rejected
claims:
(1) Reopen prosecution. Submit an
appropriate amendment of the claims so rejected or
new Evidence relating to the claims so rejected, or
both, and have the matter reconsidered by the
examiner, in which event the prosecution will be
remanded to the examiner. The new ground of
rejection is binding upon the examiner unless an
amendment or new Evidence not previously of
Record is made which, in the opinion of the
examiner, overcomes the new ground of rejection
designated in the decision. Should the examiner
reject the claims, appellant may again appeal to the
Board pursuant to this subpart.
(2) Request rehearing. Request that the
proceeding be reheard under § 41.52 by the Board
upon the same Record. The request for rehearing
must address any new ground of rejection and state
with particularity the points believed to have been
misapprehended or overlooked in entering the new
ground of rejection and also state all other grounds
upon which rehearing is sought.
Further guidance on responding to a new ground of rejection can be
found in the Manual of Patent Examining Procedure (MPEP) § 1214.01
(9th Ed., Rev. 9, Nov. 2015).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l)(iv).
REHEARING DENIED
37 C.F.R, $ 41.50(b)
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