Ex Parte Clark et al

Patent Trial and Appeal Board

Mar 26, 2013

11831985 (P.T.A.B. Mar. 26, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte MICHAEL T. CLARK and JELENA ILIC

________________

Appeal 2010-011206
Application 11/831,985
Technology Center 2100
________________

Before ERIC B. CHEN, TREVOR M. JEFFERSON, and JOHN G. NEW,
Administrative Patent Judges.

NEW, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-011206
Application 11/831,985

2
SUMMARY
Appellants file this appeal under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 1-22 as unpatentable under 35
U.S.C.§ 103(a) as being obvious over the combination of Gephardt (US
5,530,891, June 25, 1996) (“Gephardt”), Wilcox et al. (US 5,764,999, June
9, 1998) (“Wilcox”), and Deschepper et al. (US 6,199,134 B1, March 6,
2001) (“Deschepper”).
We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
Appellants’ invention is directed to a computer system, including a
system memory, a plurality of processor cores, and an input/output (I/O)
hub, that may communicate with each of the processor cores. In response
to detecting an occurrence of an internal system management interrupt
(SMI), each of the processor cores may save to a system management mode
(SMM) save state in the system memory, information corresponding to a
source of the internal SMI. In response to detecting the internal SMI, each
processor core may further initiate a I/O cycle to a predetermined port
address within the hub. The 110 hub may broadcast an SMI message to
each of the processor cores in response to receiving the 110 cycle. Each of
the processor cores may further save to the SMM save state in the system
memory, respective internal SMI source information in response to
receiving the broadcast SMI message. Abstract.

Appeal 2010-011206
Application 11/831,985

3
GROUPING OF CLAIMS

Because Appellants argue that the Examiner erred for substantially
the same reasons with respect to claims 1, 9, and 17, we select claim 1 as
representative of this group. App. Br. 5. Claim 1 recites:
1. A computer system comprising:

a system memory;

a plurality of processor cores coupled to the system
memory, wherein in response to detecting an
occurrence of an internal system management
interrupt (SMI), each of the processor cores is
configured to save to a system management mode
(SMM) save state in the system memory,
information corresponding to a source of the
internal SMI;

an input/output (I/O hub) configured to communicate
with each of the processor cores;

wherein in response to detecting the internal SMI, each
processor core is further configured to initiate an
I/O cycle to a predetermined port address within
the I/O hub;

wherein the I/O hub is configured to broadcast an SMI
message to each of the plurality of processor cores
in response to receiving the I/O cycle;

wherein each of the processor cores is further configured
to save to the SMM save state in the system
memory, respective internal SMI source
information in response to receiving the broadcast
SMI message.

App. Br. 12.

Appeal 2010-011206
Application 11/831,985

4
Appellants argue that the Examiner erred for substantially the same
reasons with respect to claims 2, 10, and 18 and that these claims are
separately patentable. App. Br. 8. We therefore select claim 2 as
representative of this group. Claim 2 recites:
2. The computer system as recited in claim 1, wherein a
selected one of the plurality of processor cores is
configured to read from the system memory, the SMM
save state of all of the processor cores to determine
within which processor core the internal SMI occurred.

App. Br. 12.

Appellants argue that the Examiner erred for substantially the same
reasons with respect to claims 3, 11, and 19, and that these claims are
separately patentable. App. Br. 9. We therefore select claim 3 as
representative of this group. Claim 3 recites:
3. The computer system as recited in claim 2, wherein an
SMI handler within the selected processor core is
configured to service the internal SMI of the processor
core within which the internal SMI occurred.

App. Br. 12.
Appellants argue that the Examiner erred for substantially the same
reasons with respect to claims 5, 13, and 21 and that these claims are
separately patentable. App. Br. 9. We therefore select claim 5 as
representative of this group. Claim 5 recites:
5. The computer system as recited in claim 4, wherein the
predetermined port address is programmed into a model
specific register of each of the processor cores during the
boot-up process by the BIOS.

App. Br. 13.

Appeal 2010-011206
Application 11/831,985

5
Appellants argue that the Examiner erred for substantially the same reasons
with respect to claims 8, 14, and 22 and that these claims are separately
patentable. App. Br. 10. We therefore select claim 8 as representative of
this group. Claim 8 recites:
8. The computer system as recited in claim 1, wherein the
information corresponding to a source of the internal
SMI comprises a bit vector having a plurality of bits each
corresponding to a respective source of an internal SMI.

App. Br. 13.

ISSUES AND ANALYSES
We address each of Appellants’ arguments seriatim, as presented in
Appellants’ Brief.

A. Rejection of claims 1, 9, and 17 under 35 U.S.C. § 103(a).
Issue 1
Appellants argue that the Examiner erred in finding that Gephardt
teaches or suggests storing in the SMM save state in memory “information
corresponding to a source” of the SMI. App. Br. 5-6. Appellants also
argue that the Examiner erred in finding that saving SMI source information
is inherent when a processor switches to SMM. App. Br. 6. We therefore
address the issue of whether the Examiner so erred.

Analysis
Appellants argue that Gephardt discusses SMM and the handling of
SMI interrupts using registers in a controller. App. Br. 6. Appellants assert
that Gephardt does not teach or suggest saving the SMI source information
Appeal 2010-011206
Application 11/831,985

6
within the SMM save state in the system memory. Id. Appellants contend
that Gephardt uses registers within a central controller to communicate
interrupt information. Id. (citing, e.g., Gephardt, Figs. 12, 13, and cols. 15-
16.
Appellants argue further that processors use an SMI handler upon
entering SMM, and because the SMI handler is a special handler that is
executed upon entering SMM, the interrupt descriptor table (IDT) is not
used to hold descriptors for SMI interrupts. App. Br. 6. Therefore, argue
Appellants, although the IDT is stored in the SMM save state area in
memory, SMI interrupt source information is not necessarily stored therein.
Id. Consequently, Appellants contend, and contra the Examiner’s findings,
the reason the processor state is saved is so that once the SMI has been
serviced, the processor can restore the processor state as it was prior to the
SMI, and NOT so that the processor can “actually servic[e] the interrupt.”
Id. (quoting Final Rej., 2).
The Examiner responds that, as an initial matter, Appellants have
mischaracterized Examiner’s findings by asserting that the Examiner finds
that it is inherent to the teachings of Gephardt to save the source
information; rather, the Examiner finds, saving the state is inherent to
Gephardt. Ans. 6.
The Examiner finds further that Gephardt explicitly teaches that the
Source ID of interrupts is stored in the processor registers, thus this is part
of the state information taught by Gephardt. Ans. 6. The Examiner finds
that Wilcox also teaches that “[f]or internally-signaled SMIs, the processor
has available source and/or specific cause of the SMI” and that “[f]or
externally-signaled SMIs, the chipset 49 includes SMI control registers that
Appeal 2010-011206
Application 11/831,985

7
must be read by the processor to determine the source of an SMI.” Ans. 7
(citing Wilcox, col. 8, ll. 32-42). The Examiner finds that Deschepper also
explicitly teaches identifying the source of the interrupt (column 12 lines
40-65).
The Examiner concludes that, since it is inherent that the processor
save state and the Source ID is part of Gephardt’s state, and that Wilcox
expressly states the source of an SMI must be identified, it would have
therefore been obvious to a person of ordinary skill in the contemporaneous
art to save this part of the state information along with the rest of the state
information, because saving state is required for interrupt handling. Ans. 6-
7.
We are persuaded by the Examiner’s reasoning and adopt it as our
own. We agree with the Examiner that Gephardt teaches that Source ID is
saved in the registers. Ans. 7. Moreover, we are persuaded by the
Examiner’s unrebutted finding that saving the state at the time of the SMI is
inherent to the teachings of Gephardt and that furthermore state is saved to
service an interrupt. Ans. 6, 7. Thus, since the source ID and is part of the
state and since Wilcox teaches or suggests that the source of an SMI must
be identified, we conclude that it would have been obvious to one of
ordinary skill in the contemporaneous art to save this information when
saving the state. We therefore conclude that the Examiner did not err in
finding that the combination of Gephardt and Wilcox teaches or suggests
storing in the SMM save state in memory “information corresponding to a
source of the internal SMI,” as recited in claim 1.

Appeal 2010-011206
Application 11/831,985

8
Issue 2
Appellants argue that the Examiner erred in finding that Deschepper
teaches the limitations of claim 1 reciting “in response to detecting the
internal SMI, each processor core is further configured to initiate an I/O
cycle to a predetermined port address within the hub” and “the I/O hub
broadcast[ing] an SMI message to each of the plurality of processor cores in
response to receiving the I/O cycle.” App. Br. 8. We therefore address the
issue of whether the Examiner so erred.

Analysis
Appellants argue that Deschepper discloses a “[s]outh bridge logic
Device” includes “trap registers” that hold device “status information” for
devices that “are powered down.” App. Br. 8. Appellants assert that the
bridge traps PCI accesses from a single CPU or other PCI device to I/O
devices that are in a low power state. Id. Moreover, Appellants contend,
the bridge device “ACPI/power management logic causes an SMI signal to
be transmitted to the processor” in response to detecting “an access to the
target that has been placed in the low power mode.” Id. (quoting
Deschepper, col. 4, ll. 14-65). Appellants argue that the predetermined
address in the I/O hub is used for just that purpose, and is not an address of
some peripheral device that has been powered down and that, furthermore,
the claimed I/O hub “broadcast[s] an SMI message” to all the other
processor cores, and does not simply generate an SMI to the one CPU in the
system.” App. Br. 8.
The Examiner responds that obviousness rejection of claim 1 was
over the combination of Gephardt, Wilcox, and Deschepper. Ans. 9. The
Appeal 2010-011206
Application 11/831,985

9
Examiner finds that Wilcox teaches or suggests that an address is used to
generate the SMI, and that “internally-signaled SMI's are all memory
mapped or I/O traps,” and that, therefore, the internal SMI’s source is an
address Id. (quoting Wilcox, col. 8 ll. 25-31). The Examiner finds that
although Wilcox does not teach or suggest that such address trapping can be
performed in a HUB, Deschepper teaches that an address can be
used in a hub to generate the SMI’s. Ans. 9. The Examiner further finds
that Gephardt teaches or suggests a “command” sent to the hub for the
purpose of broadcasting an SMI to the other cores. Id.
The Examiner concludes that it would therefore have been obvious to
one of ordinary skill in the contemporary art to have the core provide an
address signal to the HUB so as to have it generate the SMI that is
broadcast, as opposed to the processor core generating the SMI to all the
other cores. Id. An artisan of ordinary skill would have been motivated to
so combine the teachings of the prior art references because this would
allow for the HUB to handle the signaling to the other cores, leaving the
processor to have to signal only one other device (i.e., the HUB), thus
removing the additional signaling requirement from each of the processor
cores and increasing system efficiency. Id.
Appellants reply that the address of the SMI, as taught by Wilcox,
would not be the address sent to the hub. Reply Br. 5. Appellants argue
that Gephardt does send a command to the hub to tell the hub to broadcast
an SMI, and that the Deschepper teaches that the hub places addresses in a
table as peripheral devices are powered down, and simply traps on those
addresses when some device tries to normally access the peripherals
because those are considered illegal accesses and require an SMI to be
Appeal 2010-011206
Application 11/831,985

10
initiated. Id. However, argue Appellants, there is no suggestion to send the
command of Gephardt to a predetermined and dedicated port address in the
hub. Id.
We are persuaded by the Examiner’s reasoning and adopt it as our
own. “One cannot show non-obviousness by attacking references
individually where, as here, the rejections are based on combinations of
references.” In re Keller, 642 F.2d 413, 426 (C.C.P.A. 1981). In this
instance, we agree with the Examiner’s reasoning that the combination of
Gephardt, Wilcox, and Deschepper teaches the disputed limitations.
Specifically, we are persuaded that the teachings or suggestions of
Deschepper, combined with those of Gephardt and Wilcox, teaches or
suggests an address trap that causes the generation of an SMI, and that it
would have been obvious to an artisan of ordinary skill in the
contemporaneous art to use a port address in the I/O hub to generate the
global SMI because this would have eliminated any need for an extra signal
line to signal the I/O HUB for generating the broadcast SMI. Ans. 5.

B. Rejection of claims 2, 10, and 18 under 35 U.S.C. § 103(a).
Issue
Appellants argue that the Examiner erred in finding that Gephardt
teaches or suggests the limitation of claim 1 reciting added) “wherein a
selected one of the plurality of processor cores is configured to read from
the system memory, the SMM save state of all of the processor cores to
determine within which processor core the internal SMI occurred.” App.
Br. 8. We therefore address the issue of whether the Examiner so erred.

Appeal 2010-011206
Application 11/831,985

11
Analysis
Appellants argue that claim 2 requires “a selected” one of the
processor cores that “read[s] from the system memory, the SMM save
state of all of the processor cores to determine within which processor core
the internal SMI occurred,” and assert that this limitation is neither taught
nor suggested in any of the prior art references. App. Br. 8. Moreover,
argue Appellants, Gephardt teaches that the originating processor ID (i.e.,
the processor) which caused the interprocessor interrupt (IPI), and not an
SMI, is stored in a register. Id. (citing Gephardt, Table 8). Appellants
maintain that Wilcox and Deschepper both teach CPU systems and so
cannot possibly teach the features of claim 2. App. Br. 8.
The Examiner responds that all three references teach or suggest that
the processor that services the SMI determines the source of an interrupt.
Ans. 9. The Examiner finds that Wilcox teaches that “[f]or internally-
signaled SMIs, the processor has available source and/or specific cause of
the SMI” and that “[f]or externally-signaled SMIs, the chipset 49 includes
SMI control registers that must be read by the processor to determine the
source of an SMI.” Id. (citing Wilcox, col. 8, ll. 32-42). The Examiner
further finds that Deschepper also teaches or suggests identifying the source
of the interrupt. Ans. 9 (citing Deschepper, col., 12 ll. 40-65). Therefore,
the Examiner finds a “selected one” (i.e., the processor that services the
interrupt) of the plurality of processor cores is configured to read the source
information. Ans. 9. The Examiner therefore finds that all three references
teach or suggest that the processor that services the interrupt reads the
source information from where it is saved. Id.
Appeal 2010-011206
Application 11/831,985

12
Appellants reply that they disagree with the Examiner’s assertion that
a “selected one” of the cores “read[s] from the system memory, the SMM
save state of all of the processor cores to determine within which processor
core the internal SMI occurred.” Reply Br. 6. Appellants argue that all
three references simply disclose servicing an SMI and that, therefore, the
combination of references does not teach or suggest the “selected one” core
reading “the SMM save state of all of the processor cores.” Id.
We are persuaded by the Examiner’s reasoning and adopt it as our
own. As an initial matter, Appellants provide no specific definition of
“selected” in their Specification. Consequently, the Examiner may employ
the broadest reasonable meaning of the words in their ordinary usage as
they would be understood by one of ordinary skill in the art. See In re
Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). In this instance “selected”
may be reasonably defined as “chosen from a number or group by fitness or
preference.” Merriam-Webster Online Dictionary, available at
http://www.merriam-webster.com/dictionary/selected?show=1&t=
1363985686 (last visited March 22, 2013). Consequently, the Examiner’s
definition of “selected” as “the processor that services the interrupt” is not
unreasonable. See Ans. 9.
Moreover, Appellants admit that all three prior art references teach or
suggest that the references disclose identifying the source of the interrupt,
but argue that Deschepper and Wilcox are irrelevant because they only
teach single-processor systems. Reply Br. 7. As discussed supra, it is the
combination of teachings that is relevant to an obviousness analysis. We
agree with the Examiner that Gephardt teaches a plurality of processor
cores, and, when combined with the teachings of Deschepper and Wilcox,
Appeal 2010-011206
Application 11/831,985

13
teaches or suggests the limitation of claim 2 reciting “wherein a selected
one of the plurality of processor cores is configured to read from the system
memory, the SMM save state of all of the processor cores to determine
within which processor core the internal SMI occurred.” Ans. 9. We
consequently conclude that the Examiner did not err.

C. Rejection of claims 3, 11, and 19 under 35 U.S.C. § 103(a).
Issue
Appellants argue that the Examiner erred in finding that Gephardt
teaches or suggests the limitation of claim 3 reciting “wherein an SMI
handler within the selected processor core is configured to service the
internal SMI of the processor core within which the internal SMI occurred.”
App. Br. 9. We therefore address the issue of whether the Examiner so
erred.

Analysis
Appellants argue that that Gephardt does not teach or suggest
internal SMI interrupts. App. Br. 9. Additionally, Appellants argue,
Gephardt teaches servicing SMI interrupts from a power management unit.
Id. (citing Gephardt, col. 21, ll. 35-37). Therefore, Appellants contend,
Gephardt does not teach or suggest the disputed limitation.
The Examiner responds that the obviousness rejection of claim 3 is
not made in view of Gephardt alone, but is based upon a combination of the
references. Ans. 10. The Examiner finds that Wilcox teaches internal
interrupts and that Gephardt teaches the processor that receives the SMI is
the master processor. Id. Since the interrupt is internal in Wilcox, the
Appeal 2010-011206
Application 11/831,985

14
process in which the interrupt originates would be the processor to first
receive the interrupt. Id.
We agree with the Examiner. “One cannot show non-obviousness by
attacking references individually where, as here, the rejections are based on
combinations of references.” Keller, 642 F.2d at 426. It is not disputed that
Wilcox teaches internal interrupts. See Wilcox, col. 8, ll. 27-30. We agree
with the Examiner that the combination of the prior art references therefore
teaches the disputed limitation.

D. Rejection of claims 5, 13, and 21 under 35 U.S.C. § 103(a).
Issue
Appellants next argue that the Examiner erred in finding that Wilcox
neither teaches nor suggests the limitation of claim 5 reciting “wherein the
predetermined port address is programmed into a model specific register of
each of the processor cores during the boot-up process by the BIOS.” We
therefore address whether the Examiner so erred.

Analysis
Appellants argue that Wilcox teaches or suggests I/O traps that
generate internal SMIs in the processor. App. Br. 9. Appellants assert that
this is different from generating a global SMI in response to an I/O cycle to
a predetermined port address of an I/O hub. Id. Appellants contend further
that such I/O traps are a VSA extension for virtualization of peripheral
software functions. Id. (citing Wilcox at col. 9, ll. 6-20). Appellants argue
that there would therefore be no reason to store in BIOS I/O trap addresses
for a software system that may change from version to version. App. Br. 9.
Appeal 2010-011206
Application 11/831,985

15
The Examiner responds that Wilcox teaches or suggests I/O traps and
BIOS, that Gephardt teaches or suggests a global SMI, and that Deschepper
teaches or suggests that the trap can be in a hub. Ans. 10. Consequently,
the Examiner finds, the combination of the three references teaches or
suggests generating a global SMI trap in the hub. Id.
Appellants reply that the Examiner’s assertion that Wilcox teaches or
suggests I/O traps and BIOS does not reveal why would someone of skill in
the art be motivated to have the BIOS program the predetermined address
into a model specific register, as required by claim 5. Reply Br. 7.
We are not persuaded by Appellants’ arguments. Motivation to
combine has been discussed supra. We agree with the Examiner’s finding
that Wilcox teaches a “trapped” address for an I/O cycle but is silent upon
how the initial determination that the address should be “trapped.” Ans. 5.
Moreover we agree with the Examiner’s finding that Wilcox also teaches
BIOS but does not give any description of what is provided by the BIOS.
Id. However, we also agree with the Examiner’s conclusion that it would
have been obvious to one of ordinary skill in the contemporaneous art to
store the “Trap” addressees in the BIOS because this would have thereby
provided an initial trap value. Id.

E. Rejection of claims 8, 14, and 22 under 35 U.S.C. § 103(a).
Issue
Appellants argue that the Examiner erred in finding that Gephardt
does not teach or suggest the limitation of claim 8 reciting “wherein the
information corresponding to a source of the internal SMI comprises a bit
vector having a plurality of bits each corresponding to a respective source
Appeal 2010-011206
Application 11/831,985

16
of an internal SMI.” App. Br. 10. We therefore address the issue of
whether the Examiner so erred.

Analysis
Appellants argue that the entry in Table 8 of Gephardt refers to the
originating processor ID of an interprocessor interrupt (IPI), which is the
processor ID of the processor that generated or has scheduled an IPI, and
not the source of an internal SMI within a processor. App. Br. 10.
Furthermore, argue Appellants, the processor ID of Gephardt does not
constitute a “bit vector” in which each bit corresponds “to a respective
source of an internal SMI.”
We refer Appellants to our discussion supra with respect to why we
affirm the Examiner’s finding that the combination of the prior art
references teaches “information corresponding to a source of the internal
SMI.” Moreover, Appellants’ Specification states that [i]n response to
detecting an occurrence of an internal system management interrupt (SMI),
each of the processor cores may save to a system management mode
(SMM) save state in the system memory, information such as a bit vector,
for example, corresponding to a source of the internal SMI,” but provides
no explicit definition of “bit vector” We therefore adopt the broadest
reasonable definition of the phrase “source of the internal SMI comprises a
bit vector having a plurality of bits each corresponding to a respective
source of an internal SMI” as corresponding to the location address taught
by Deschepper as the source of an interrupt. See Deschepper, col. 12, ll.
45-49 (“The master controller may be programmed in the fully nested mode
to permit the slave controller to send the correct interrupt vector back to the
Appeal 2010-011206
Application 11/831,985

17
CPU identifying the source of the interrupt”); see also Ans. 7. We
consequently conclude that the Examiner did not err in finding that the
combination of prior art references teaches or suggests the limitation of
claim 8 reciting “wherein the information corresponding to a source of the
internal SMI comprises a bit vector having a plurality of bits each
corresponding to a respective source of an internal SMI.”

DECISION

The Examiner’s rejection of claims 1-22 as unpatentable under 35
U.S.C. 103(a) is affirmed.

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a) (1)(iv) .

AFFIRMED

ke