Ex Parte Clark et al

Patent Trial and Appeal Board

Apr 24, 2017

13459964 (P.T.A.B. Apr. 24, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/459,964 04/30/2012 Lawrence T. Clark 1135-032 6720
27820 7590 04/26/2017
WITHROW & TERRANOVA, P.L.L.C.
106 Pinedale Springs Way
Cary, NC27511
EXAMINER
CALDWELL, ANDREW T
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
04/26/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents @ wt-ip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte LAWRENCE T. CLARK, SIDDHESH MHAMBREY, and
SATENDRA KUMAR MAURYA
Appeal 2016-002785
Application 13/459,9641
Technology Center 2100
Before JAMES R. HUGHES, ERIC S. FRAHM, and
JAMES W. DEJMEK, Administrative Patent Judges.
DEJMEK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1—3, 6, 8—12, 15, 16, and 21—24.2 Claims 4, 18, and 25 have been
canceled. App. Br. 23, 27, 29. We have jurisdiction over the remaining
pending claims under 35 U.S.C. § 6(b).
We affirm-in-part.
1 Appellants identify the Arizona Board of Regents for and on behalf of
Arizona State University as the real party in interest. App. Br. 1.
2 The Examiner has withdrawn the rejection of claims 5, 7, 13, 14, 19, and
20. Ans. 2.
Appeal 2016-002785
Application 13/459,964
STATEMENT OF THE CASE
Introduction
Appellants’ claimed invention is directed to “superscalar pipelines and
instruction issue circuits within microprocessors.” Spec. 12. According to
the Specification, a superscalar processor allows for the execution of
multiple instructions per clock cycle. Spec. 13. In a disclosed embodiment,
an instruction issue circuit is configured to issue multiple instructions within
a superscalar pipeline. Spec. 17. The disclosed instruction issue circuit
comprises an instruction queue that stores instructions ordered in accordance
with an execution priority. Spec. 17. The instruction queue further
comprises a ready generation circuit to generate ready signals for each
instruction to indicate whether the instruction is ready for execution. Spec.
17. Further within a disclosed embodiment, the ready signals are split into a
plurality of groups such that the groups of ready signals may be processed in
parallel. Spec. 1 8.
Claims 1 and 8 are exemplary of the subject matter on appeal and are
reproduced below with the disputed limitations emphasized in italics'.
1. An instruction issue circuit, comprising:
an instruction queue operable to store a plurality of
instructions so that the plurality of instructions are ordered in
accordance with an instruction execution priority;
a ready generation circuit operably associated with the
instruction queue to generate a plurality of ready signals, wherein
each ready signal of the plurality of ready signals indicates
whether a different corresponding one of the plurality of
instructions stored by the instruction queue is ready for
execution;
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a plurality of group blocks for generating a plurality of
group outputs, each group block of the plurality of group blocks
being operable to:
receive a different group of the plurality of ready signals
that correspond to a different group of the plurality of
instructions; and
generate a corresponding group output of the plurality of
group outputs based on the different group of the plurality of
ready signals, wherein the corresponding group output indicates
a group set within the different group of the plurality of
instructions having a highest instruction execution priority
among the different group of the plurality of instructions that are
ready for execution;
a global instruction block configured to:
receive the plurality of group outputs from the plurality of
group blocks; and
generate a global grant output based on the plurality of
group outputs, wherein the global grant output indicates a global
set of the plurality of instructions having a highest instruction
execution priority among the plurality of instructions that are
ready for execution.
8. The instruction issue circuit of claim 1, wherein the
plurality of group blocks comprise:
a first plurality of shifters configured to generate the
plurality of group outputs, each shifter of the first plurality of
shifters being operable to generate the corresponding group
output of the plurality of group outputs such that the
corresponding group output comprises a first group of one-hot
outputs; and
wherein, for each one-hot output in the first group of one-
hot outputs, the one-hot output in the first group of one-hot
outputs corresponds to a corresponding instruction in the
different group of the plurality of instructions and indicates a
number of the different group of the plurality of instructions
having an instruction execution priority that is higher than an
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instruction execution priority of the corresponding instruction
and that are also ready for execution.
The Examiner’s Rejections
1. Claims 1—3, 6, 8—12, 17, and 21—24 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Jensen (US 2009/0271592
Al; Oct. 29, 2009) and Zaidi et al. (US 6,065,105; May 16, 2000) (“Zaidi”).
Final Act. 3—25.
2. Claims 15 and 16 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Jensen, Zaidi, and Yoshida (US 6,260,135 Bl;
July 10, 2001). Final Act. 25-27.
Issues on Appeal
1. Did the Examiner err in finding the combination of Jensen and
Zaidi teaches or suggests a global instruction block configured to generate a
global grant output that “indicates a global set of the plurality of instructions
having a highest instruction execution priority among the plurality of
instructions that are ready for execution,” as recited in claim 1?
2. Did the Examiner err in finding the combination of Jensen and
Zaidi teaches or suggests a one-hot output that “indicates a number of the
different group of the plurality of instructions having an instruction
execution priority that is higher than an instruction execution priority of the
corresponding instruction and that are also ready for execution,” as recited in
claim 8?
3. Did the Examiner err in finding the combination of Jensen and
Zaidi teaches or suggests “a one-hot output that indicates the number of the
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different group of the plurality of instructions that are ready for execution,”
as recited in claim 12?
ANALYSIS3
Claims 1—3, 6, 11, 15—17, and 21—24
In rejecting claim 1, the Examiner finds Jensen teaches, inter alia, the
claimed global instruction block. Final Act. 5—6 (citing Jensen 1106,
Figs. 2, 7). Additionally, the Examiner finds Jensen teaches the global
instruction block generates a global grant output that indicates a global set of
the plurality of instructions having a highest instruction execution priority.
Final Act. 6.
Contrary to the Examiner’s findings, Appellants assert Jensen does
not teach a global grant output that indicates a global set of instructions
having a highest execution priority, but rather selects a single instruction.
App. Br. 11—15; Reply Br. 2—3. Further, Appellants contend that even if
Jensen did select a set of instructions, the selected set would not have the
highest execution priority because the final multiplexer (724) in Figure 7 of
Jensen, as identified by the Examiner, could only select the highest
execution instructions from among those that were previously selected by
multiplexers in earlier stages of the tree-design of Jensen. App. Br. 12.
3 Throughout this Decision, we have considered the Appeal Brief, filed
May 18, 2015 (“App. Br.”); the Reply Brief, filed January 12, 2016 (“Reply
Br.”); the Examiner’s Answer, mailed November 12, 2015 (“Ans.”); and the
Final Office Action, mailed December 23, 2014 (“Final Act.”), from which
this Appeal is taken.
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Figure 7 of Jensen is illustrative and is reproduced below:
Fig. 7
Figure 7 of Jensen is a block diagram of a dispatch scheduler and instruction
selection logic. Jensen 124.
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Jensen teaches the instruction selection logic (202) includes a plurality
of multiplexers (724) arranged in a tree-structure such that the multiplexers
illustrated on the left portion of instruction selection logic (202) each receive
an instruction (206) from two different thread contexts. Jensen 1106. Each
instruction also has an associated priority (denoted as DS_TC_priority
(208)). Jensen 1106. Jensen also teaches that the comparator (714)
associated with each multiplexer (724) receives the corresponding
DS_TC_priority for the instructions presented to the multiplexer (724) to
control the multiplexer and select the instruction with the higher priority
value. Jensen 1106. Further, Jensen teaches: “The selected instructions 206
and DS_TC_priorities 208 propagate down the tree until the final mux [(i.e.,
multiplexer)] 724 selects the selected instruction 204 of FIG. 2 with the
highest DS_TC_priority 208 for provision to the execution pipeline.” Jensen
1106.
The Examiner finds, and we agree, the selected instruction (204)
corresponds to the claimed global group output, which indicates a thread
(i.e., a global set of instructions) having a highest execution priority (as
indicated by the DS_TC_priority value) among the plurality of instructions
that are ready for execution. Ans. 5 (citing Jensen 1144, 101, 106, 107). As
taught by Jensen, n instructions, each having an associated thread context
priority, are arranged in pairs and presented to a first stage of multiplexers
wherein the instruction having a higher priority is output from the
multiplexer (along with its thread context priority) and is input to a
subsequent multiplexer stage until a final instruction having the highest
thread context priority is selected. Additionally, the Examiner finds, and we
agree, Jensen teaches “the selection logic may be configured to operate such
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that multiple instructions from different threads are selected per clock
cycle,” i.e., in a superscalar implementation. Ans. 5 (citing Jensen | 56).
For the reasons discussed supra, we are unpersuaded of Examiner
error. Accordingly, we sustain the Examiner’s rejection of claim 1 and, for
similar reasons, the rejection of independent claims 17 and 23, which recite
similar limitations and were not argued separately. See App. Br. 19-20.
Additionally, we sustain the Examiner’s rejections of claims 2, 3, 6, 11, 15,
16, 21, 22, 24, which depend therefrom and were not argued separately. See
App. Br. 19-20.
Claims 8—10 and 12
Claim 8 recites, in relevant part, a one-hot output which “indicates a
number of the different group of the plurality of instructions having an
instruction execution priority that is higher than an instruction execution
priority of the corresponding instruction.” Claim 12 recites, in relevant part,
“a one-hot output that indicates the number of the different group of the
plurality of instructions that are ready for execution.”
Appellants contend the round-robin bit of Jensen, as relied on by the
Examiner, is used to select a thread if more than one thread context had an
instruction ready for execution and the same priority value. App. Br. 18
(citing Jensen || 108—110).
In response, the Examiner finds “[wjhen two threads in contention at
the same mux 724 have the same PM_TC_priority, the round-robin bit is
used to indicate the thread with the higher execution priority among the two
threads.” Ans. 6. Additionally, the Examiner explains because each thread
is represented by its own round-robin bit, the round-robin bit “indicates the
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number of the different group of the plurality of instructions that are ready
for execution.” Ans. 7.
Appellants further respond and contend merely representing a thread
by a round-robin bit does not indicate the number of instructions ready for
execution, much less a “number,” as required by the claim language. Reply
Br. 4—5.
We find Appellants’ arguments persuasive of Examiner error.
Although we agree with the Examiner that Jensen teaches the use of a round-
robin bit to select (i.e., indicate) between two threads having the same
PM_TC_priority the thread with the higher execution priority (see, e.g.,
Jensen 1110), the Examiner has not provided sufficient technical reasoning
or explanation to support a finding that the round-robin bit indicates a
number of the group of the plurality of instructions having a higher
execution priority.
For the reasons discussed supra, we are constrained by the record
before us and do not sustain the Examiner’s rejection of claims 8 and 12.
Additionally, and for similar reasons, we do not sustain the Examiner’s
rejection of claims 9 and 10, which depend from claim 8.
DECISION
We affirm the Examiner’s decision rejecting claims 1—3, 6, 11, 15—17,
and 21-24.
We reverse the Examiner’s decision rejecting claims 8—10 and 12.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).
AFFIRMED-IN-PART
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