Ex Parte Chun

Patent Trial and Appeal Board

Jun 21, 2018

12828815 (P.T.A.B. Jun. 21, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/828,815 07/01/2010 Christopher Kong Yee Chun
12371 7590 06/25/2018
Muncy, Geissler, Olds & Lowe, P.C./QUALCOMM
4000 Legato Road, Suite 310
Fairfax, VA 22033
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
QC091055 7483
EXAMINER
GRULLON, FRANCISCO A
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
06/25/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
meo.docket@mg-ip.com
meo@mg-ip.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHRISTOPHER KONG YEE CHUN
Appeal2018-000636
Application 12/828,815
Technology Center 2100
Before CARLA M. KRIVAK, HUNG H. BUI, and JON M. JURGOV AN,
Administrative Patent Judges.
JURGOV AN, Administrative Patent Judge.
DECISION ON APPEAL
Appellant 1 seeks review under 35 U.S.C. § 134(a) from a Final
Rejection of claims 1-3, 5-9, and 11-34, which are all the claims pending in
the application. We have jurisdiction under 35 U.S.C. § 6(b ).
We AFFIRM-IN-PART. 2
1 Appellant identifies QUALCOMM Incorporated as the real party in
interest. (App. Br. 3.)
2 Our Decision refers to the Specification ("Spec.") filed July 1, 2010; the
Final Office Action ("Final Act.") mailed January 27, 2017; the Appeal
Brief ("App. Br.") filed May 1, 2017; the Examiner's Answer ("Ans.")
mailed September 22, 2017; and the Reply Brief ("Reply Br.") filed October
25, 2017.
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CLAIMED INVENTION
The claims are directed to "mobile device memory architectures," and
methods for "improving the power cycling characteristics of a mobile device
using various volatile and non-volatile memory configurations." (Spec. i-f 1.)
In one embodiment, "a processor [is] coupled to [a] memory controller,
where the processor may address both the non-volatile memory and the
volatile memory utilizing a continuous memory map." (Spec. i-f 8.) In
another embodiment, "a processor [is] coupled to [a] memory controller,
where the processor may address the volatile memory during normal
operation," and a "shadow copy controller ... coupled to the non-volatile
memory and the memory controller" to "copy information stored in a
designated portion of the volatile memory into the non-volatile memory."
(Spec. i-f 9.)
Claims 1, 9, 21, 25, 27, and 29 are independent. Claims 1and9,
reproduced below, are illustrative of the claimed subject matter:
1. A mobile device, comprising:
a volatile memory;
a non-volatile memory comprising a Magnetoresistive
Random Access Memory (MRAM);
a memory controller functionally coupled to the non-
volatile memory and the volatile memory; and
a processor coupled to the memory controller,
wherein the processor addresses both the non-volatile
memory and the volatile memory substantially at the same time
utilizing a continuous memory map, and
wherein the processor writes system-state information to
the non-volatile memory and/or reads the system-state
information from the non-volatile memory.
9. A mobile device, comprising:
a volatile memory;
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a non-volatile memory compnsmg a Magnetoresistive
Random Access Memory (MRAM);
a memory controller coupled to the volatile memory;
a processor coupled to the memory controller, wherein the
processor addresses the volatile memory during a normal
operation; and
a shadow copy controller coupled to the non-volatile
memory and the memory controller,
wherein the shadow copy controller copies information
stored in a designated portion of the volatile memory into the
non-volatile memory during the normal operation, and
wherein the shadow copy controller copies the information
stored in the designated portion of the volatile memory
substantially at the same time as the information is written into
the volatile memory by the memory controller during the normal
operation.
(App. Br. 31-33, Claims App.)
REJECTIONS & REFERENCES
(1) Claim 32 stands rejected under 35 U.S.C. § l 12(a) or
35 U.S.C. § 112, first paragraph (pre-AIA), as failing to comply with the
written description requirement. (Final Act. 4--5.)
(2) Claims 1, 2, 5, 8, 9, 11-14, 16, 17, 20, 21, 23, 25, 27, 29, and
31-34 stand rejected under 35 U.S.C. § 103(a) based on Aho et al. (US
2001/0019509 Al, published Sept. 6, 2001, "Aho"), Best (US 2010/0110748
Al, published May 6, 2010), and Kilbuck et al. (US 2005/0204091 Al,
published Sept. 15, 2005, "Kilbuck"). 3 (Final Act. 6-16.)
3 The Examiner's rejection cites to US 2001/0019509 Al "as the USPTO
equivalent of the EPO publication EP 1 132 819 A2 in the same patent
family, hereinafter Aho." (Final Act. 6.) We therefore refer to US
2001/0019509 Al ("Aho") in this Decision.
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(3) Claims 3, 15, and 24 stand rejected under 35 U.S.C. § 103(a)
based on Aho, Best, Kilbuck, and Liu et al. (US 2010/0080048 Al,
published Apr. 1, 2010, "Liu"). (Final Act. 16-17.)
(4) Claims 6, 7, 18, and 19 stand rejected under 35 U.S.C. § 103(a)
based on Aho, Best, Kilbuck, and Maeda et al. (US 8,127,168 B2, issued
Feb. 28, 2012, "Maeda"). (Final Act. 17-20.)
(5) Claims 22, 26, 28, and 30 stand rejected under
35 U.S.C. § 103(a) based on Aho, Best, Kilbuck, and Davis (US 4,959,774,
issued Sept. 25, 1990). (Final Act. 20-21.)
ANALYSIS
Rejection of Claim 32 under 35 U.S.C. §§ l 12(a) or 112 (pre-AJA), First
Paragraph:
Written Description
Claim 32 depends from claim 1, and further recites "wherein the
processor does not write the system-state information to the volatile
memory." That is, claim 32 requires the system-state information-written
to or read from the non-volatile memory (per base claim 1 }-is not written
to the volatile memory.
The Examiner finds the Specification does not provide a written
description to support the negative limitation of claim 32 reciting the
processor "does not write the system-state information to the volatile
memory." (Final Act. 4--5; see also Ans. 16-17 (emphasis added).)
We disagree with the Examiner's findings. As Appellant explains,
paragraphs 29 and 31 of the originally filed Specification support the
limitation of claim 32. (App. Br. 29.)
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We have reviewed Appellant's Specification and concur with
Appellant's argument that the Specification demonstrates Appellant
possessed "the processor does not write the system-state information to the
volatile memory," as recited in claim 32. For example, paragraph 29 in
Appellant's Specification describes
[a] continuous addressing memory map 260 may be divided
wherein one portion of the map can be associated with volatile
memory, and another portion of the map can be associated with
non-volatile memory. The non-volatile portion of the map may
be reserved for storing information associated with the system
state, security, digital rights management, or other information
that can desireable[ sic] to preserve in the event of an
uncontrolled power disruption. The other portion of the map
may be associated with volatile memory, and can be used to
store ... other information, includ[ing] data which is not
critical to security or the state of the system.
(Spec. i-f 29 (emphasis added).) Thus, paragraph 29 in the Specification
provides "the non-volatile memory may be reserved for system state
information" not written to the volatile memory that is "used to store other
information." (App. Br. 29.) The Specification further explains
the processor 210 may access both volatile memory 240 and
nonvolatile memory 250 using [the] continuous memory map
260. The continuous memory map 260 can be randomly
accessed by a set of address values. On [ e] range of address
values may map to the volatile memory map 264
(corresponding to physical volatile memory 240), and another
range of values may map to the non-volatile memory map 265
(corresponding to physical non-volatile memory 250). The
processor may select which data to store to protect from power
disruptions by selecting the appropriate memory addresses
corresponding to non-volatile memory map 265. The types of
data which the processor may wish to select for storage in non-
volatile memory 250 may include system state data, security
data, Digital Rights Management (DRM) data, or any other data
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that should be preserved when power is interrupted to the
mobile device 200.
(Spec. i-f 31 (emphasis added).) Thus, certain system-state information (data
that should be preserved when power is interrupted) is written to the non-
volatile memory's range of addresses that are different from the volatile
memory's range of addresses, i.e., the system-state information is not
written to the volatile memory. We find the Specification demonstrates
Appellant possessed the claimed "processor does not write the system-state
information to the volatile memory," as recited in claim 32.
Accordingly, we do not sustain the Examiner's rejection of claim 32
under the "written description" requirement of 35 U.S.C. § 112.
Rejection of Claims 1-3 and 5---8
under 35 US.C. § 103(a)
With respect to claim 1, the Examiner finds the combination of Aho
and Best teaches the claimed processor utilizing a continuous memory map.
(Final Act. 11-12.) Particularly, the Examiner finds Aho teaches a
processor addresses both a non-volatile memory and a volatile memory
substantially at the same time utilizing a continuous memory map. (Final
Act. 12 (citing Aho i-f 28).) The Examiner further finds Best's paragraph 21
discloses "[ d]ata may similarly be transferred in the opposite direction from
the non-volatile die ... to the volatile storage die ... via [an] inter-die data
path" to restore the state of the volatile storage die to a pre-power-down or
pre-sleep condition, thereby suggesting a processor reading system-state
information from the non-volatile memory as claimed. (Final Act. 10 (citing
Best i-fi-12, 12, and 21).)
Appellant contends Best cannot be combined with Aho to teach the
claimed processor "utilizing a continuous memory map" because Best
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teaches away from and "diametrically opposes the continuous memory
map feature of independent claim 1." (Reply Br. 6.)4 Particularly,
Appellant argues
[t]he portion of [0021] of Best relied upon by the Office is in
the context of implementing memory shadowing described
above with respect to FIG. 5. Memory shadowing by definition
requires an overlap between the address ranges of the volatile
and non-volatile memories as Best illustrates in FIG. 6.
Since the memory shadowing function by definition requires
an overlap between the address ranges of the volatile and non-
volatile memories, Best diametrically opposes the continuous
memory map feature of independent claim 1.
(App. Br. 24 and Reply Br. 6.)
We do not agree with Appellant's argument. In this regard, we note
Best's description of data being "transferred in the opposite direction from
the non-volatile die ... to the volatile storage die ... via [an] inter-die data
path" (see Best i-f 21) is not restricted to a memory shadowing embodiment
with overlapped address ranges as Appellant argues. (See App. Br. 24.)
Rather, Best's paragraph 21 describes data transfer in Best's Figures 2 and 3
illustrating "hybrid memory architectures" in which "the volatile and non-
volatile storage devices have been assumed to have non-overlapping address
ranges" (thus suggesting a continuous memory map). (See Best i-fi-124, 17
("FIG. 2 illustrates an embodiment of a hybrid, composite memory device
with the shared interface circuitry" describing "one embodiment, referred to
herein as the hybrid storage embodiment, [in which] non-overlapping
address ranges apply to each of the storage dice 101 and 103 to form the
4 We count the last six pages of the Reply Brief (which are not numbered)
continuing from page 1 (which is numbered).
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overall addressable range of the composite memory device."), 21 ("FIG. 3
illustrates an embodiment of a data control/steering circuit 150 that may be
used to implement the data control/steering circuit 131 of FIG. 2.")
(emphasis added); see also Final Act. 12.)
Thus, Best's data being "transferred in the opposite direction from the
non-volatile die ... to the volatile storage die ... via [an] inter-die data
path" (see Best i-f 21) does not "lead away from," but rather teaches and
suggests the claimed processor reading system-state information from the
non-volatile memory and addressing the non-volatile and volatile memories
using a continuous memory map. (Final Act. 12; see also Ans. 9--10 and
Reply Br. 6.)
Thus, Appellant has failed to persuade us the claimed invention
distinguishes over the prior art relied on by the Examiner. We, therefore,
sustain the Examiner's rejection of independent claim 1.
No separate arguments are presented for dependent claims 2, 5, and 8.
(App. Br. 25.) Accordingly, for the reasons stated with respect to
independent claim 1, we sustain the rejection of these dependent claims. See
37 C.F.R. § 41.37(c)(l)(iv).
With respect to dependent claims 3, 6, and 7, Appellant provides
substantially the same arguments as for claim 1, and additionally argues that
Liu and Maeda do not cure the alleged deficiencies of Aho, Best, and
Kilbuck. (App. Br. 27-28.) As we find Aho, Best, and Kilbuck are not
deficient, Liu and Maeda are not needed to cover any deficiency. Therefore,
we sustain the rejection of dependent claims 3, 6, and 7 for the reasons
stated with respect to independent claim 1.
Rejection of Claims 9 and 11-31
under 35 USC§ 103(a)
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With respect to claim 9, Appellant contends Aho, Best, and Kilbuck,
alone or in combination, fail to teach or suggest a shadow copy controller
that copies information stored in a designated portion of the volatile memory
into the non-volatile memory substantially at the same time as the
information is written into the volatile memory by the memory controller,
during a normal operation, as claimed. Particularly, Appellant contends
Best's memory shadowing operation transfers information into a non-
volatile memory (Flash memory 101) in response to a "write-back trigger
[that] does NOT concurrently occur with each write to the DRAM 103
[Best's volatile memory]"; rather, Best exhibits "a significant time lapse
between when data is written to the DRAM 103 and when the same data is
transferred to the Flash memory 101" from the DRAM, the time lapse being
"critical to maintain the speed" of Best's hybrid memory device. (App. Br.
18, 20 (citing Best i-fi-12, 12, 24--25, Figs. IA and 5) (emphasis added).)
Appellant then reasons, "modifying [Best's] hybrid memory device with
Kilbuck's write-through caching such that each write to the DRAM 103
[Best's volatile memory] and a corresponding write to the Flash memory
101 [Best's non-volatile memory] occur together" renders Best
unsatisfactory for its intended purpose. (App. Br. 20-21 (emphasis added).)
Appellant asserts "Best's explicit purpose is to provide a hybrid memory
device that ... has both speed and non-volatility," and "the [Examiner's]
suggested modification would result in the speed of [Best's] hybrid memory
device being slowed down to the speed of the Flash memory [which]
completely destroys Best's purpose." (App. Br. 20.)
We are not persuaded of Examiner error as these arguments are
speculative, i.e., there is insufficient evidence to demonstrate that speed of
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Best's device is conditioned by a large time lapse (or a lapse incompatible
with the claimed "substantially at the same time") between data writing to
DRAM and data transfer to Flash. (See App. Br. 18.) Rather, Best teaches
that data written to DRAM (volatile memory) is copied to Flash (non-
volatile) memory "in response to a triggering event referred to herein as a
write-back trigger," where
[t]he write-back trigger itself may include any number or
combination of stimuli, including detecting that the write-back
table has a threshold number of valid entries; periodically
performing write-back (e.g., after every so many writes to the
non-volatile storage and/or after a predetermined or
configurable amount of time has elapsed); detecting a power-
loss or power-down signal or event (i.e., performing all
necessary write-backs-an operation referred to herein as
flushing the write-back table-as part of power down),
receiving an explicit command to flush the write-back table or
otherwise perform one or more write-back operations and so
forth.
(See Best i-fi-124, 26 (emphasis added).) That is, any number or combination
of stimuli may dictate Best's time delay between data writing to DRAM and
data copying to Flash. Thus, Best's time delay is not necessarily a long
delay incompatible with Appellant's claim 9. Rather, Best's time delay is
commensurate with claim 9's "substantially at the same time" and with the
broad description of "substantially at the same time" in Appellant's
Specification. 5 (Ans. 4 (citing Spec. Figs. 3--4).)
5 Appellant's Specification does not provide an explicit and exclusive
definition of the term "substantially at the same time"-a term introduced
into claim 9 from Appellant's original claim 10. The Specification merely
provides discussion of non-limiting examples of "substantially at the same
time." For example, the Specification provides "[t]he shadowed portion of
the volatile memory map 364 may be copied into the non-volatile memory
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Appellant's argument that the combination of Aho, Best, and Kilbuck
would render Best unsatisfactory for its intended purpose is also
unpersuasive. (App. Br. 17, and 20-21.) Particularly, there is insufficient
evidence to demonstrate that incorporating the teachings of Best and
Kilbuck into Aho would require Best's device to "slow[] down to the speed
of the Flash memory" and "perform no better than a Flash memory alone"
as asserted by Appellant. (See App. Br. 20-21.) Appellant's support for
these contentions relies upon Appellant's previous argument regarding a
large time lapse in Best. (App. Br. 18, 20.) As discussed supra, we are not
persuaded that Best requires a large time lapse (between data writing to
DRAM and data copying to Flash).
Appellant's contentions regarding the combination of Aho, Best, and
Kilbuck also misstate the Examiner's rejection. Particularly, Appellant
argues "if Aho and Best are modified as the Office suggests, then each write
to the DRAM 103 [Best's volatile memory] and the corresponding write to
the Flash memory 101 [Best's non-volatile memory] would occur together."
(App. Br. 20 (emphasis added).) However, neither claim 9, nor the
Examiner's rejection requires data writes to volatile and non-volatile
memories to occur together; rather, the Examiner's rejection (and claim 9)
requires data writes to volatile and non-volatile memories to occur
"substantially at the same time," which may include a time delay. (Ans. 4--
5; see also Final Act. 8.)
Appellant also argues the Examiner's rejection relies on
impermissible hindsight because the rejection's reasoning is dependent on
as its state is changed, thus providing a continuous 'back-up' from data loss
resulting from a power disruption." (See Spec. i-fi-135, 37, and 40.)
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"information gleaned solely from Appellant's Specification" that
Kilbuck's non-volatile MRAM and Best's volatile DRAM have
"comparable speeds." (Reply Br. 3--4.) We do not agree. The Examiner
has articulated reasoning (for combining Best and Kilbuck) that is not
gleaned from Appellant's Specification. (See Final Act. 8 (citing Kilbuck
i-fi-133, 35, and 42).) Additionally, Appellant has not explained why a skilled
artisan would not have combined a non-volatile MRAM with a volatile
memory, as in claim 9. In fact, Kilbuck's Figure 3B shows it is known to
combine a non-volatile MRAM with a volatile memory (SDRAM) in one
device. (See Kilbuck Fig. 3B; see also Ans. 5 (citing Kilbuck i130).)
Appellant also argues Aho, Best, and Kilbuck do not teach or suggest
"a memory controller coupled to the volatile memory" and "a shadow
copy controller coupled to the non-volatile memory and the memory
controller" as claimed. (App. Br. 21; see also Reply Br. 5.) Particularly,
Appellant argues "Best does NOT show the controller device whatsoever
and does not provide any details regarding the controller device." (App. Br.
22.) We do not agree. Instead, we agree with the Examiner that Best's
Figure 3 teaches and suggests a memory controller (DRAM control circuit
129) coupled to a volatile memory (DRAM memory array die), and a
shadow copy controller (non-volatile control circuit 137) coupled to a non-
volatile memory (non-volatile (NV)/Flash memory array die) and the
memory controller (129). (Ans. 8 (citing Best i-fi-f 12, 25, 28-29, and Fig. 3).)
Appellant's arguments have not persuaded us of error in the
Examiner's rejection of claim 9. Therefore, we sustain the Examiner's
rejection of independent claim 9 and the Examiner's rejection of
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independent claims 21, 25, 27, and 29 on the same basis as claim 9 (App. Br.
21; see also Reply Br. 2, 5), for the reasons stated above.
No separate arguments are presented for dependent claims 11-14, 16,
17, 20, 23, and 31. (App. Br. 25.) Accordingly, for the reasons stated with
respect to independent claims 9, 21, 25, 27, and 29, we sustain the rejection
of these dependent claims. See 37 C.F.R. § 41.37(c)(l)(iv).
With respect to dependent claims 15, 18, 19, 22, 24, 26, 28, and 30,
Appellant provides substantially the same arguments as for claims 9, 21, 25,
27, and 29, and additionally argues that Liu, Maeda, and Davis do not cure
the alleged deficiencies of Aho, Best, and Kilbuck. (App. Br. 27-28.)
Because we find Aho, Best, and Kilbuck are not deficient, Liu, Maeda, and
Davis are not needed to cure any deficiency, and therefore we sustain the
rejection of dependent claims 15, 18, 19, 22, 24, 26, 28, and 30 forthe
reasons stated with respect to the independent claims.
Rejection of Claim 32
under 35 USC§ 103(a)
With respect to claim 32, the Examiner finds "the additional content
of this claim further corresponds substantially to that of Claim 9," and
rejects claim 32 "for the same reasons as presented in Claim 9." (Final Act.
16.) Appellant argues that the claim 9 rejection is not relevant to the
features of claim 32. (App. Br. 25.) We agree, as claim 32 does not depend
from claim 9, and does not recite features of claim 9.
In the Answer, the Examiner interprets claim 32 "along the lines of
claim 1 ['s] 'processor writes system-state information to the non-volatile
memory"' for which Best was cited as "suggesting that the processor writes
system-state information to the non-volatile memory and/or reads system-
state information from the non-volatile memory." (Ans. 12 (citing Best i-fi-12,
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12, 21, and 24 ). ) However, as Appellant has already explained in the Appeal
Brief, Best's paragraph 21 does not teach what is recited in claim 3 2-that
"the processor does not write the system-state information to the volatile
memory." (App. Br. 25-26.) Rather, Best's paragraph 21 "restor[es] 'the
state of the volatile storage die 103' [which] means that the information is in
fact written to the volatile storage. Otherwise, there would be NO need to
'restore the state of the volatile storage."' (App. Br. 26 (emphasis added).)
We agree with Appellant. Best's paragraph 21 states "[d]ata may
similarly be transferred in the opposite direction from the non-volatile die
... to the volatile storage die," which does not teach a processor does not
write the system-state information to the volatile memory, as recited in claim
32. (See Best i-f 21 (emphasis added).) Best's paragraph 24 (cited by the
Examiner) describes volatile and non-volatile storage devices having "non-
overlapping address ranges," but does not disclose a processor not writing
system-state information to the volatile memory, as claimed. (See Best
,-r 24.)
As the Examiner has not identified sufficient evidence to support the
rejection of claim 32, we do not sustain the Examiner's§ 103(a) rejection of
claim 32.
Rejection of Claims 33 and 34
under 35 USC§ 103(a)
Claim 3 3 depends from claim 9, and further recites "the shadow copy
controller directly interfaces with the non-volatile memory," and "the
memory controller directly interfaces with the volatile memory and
indirectly interfaces with the non-volatile memory through the shadow copy
controller."
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Appellant argues Aho, Best, and Kilbuck do not disclose the
controllers recited in claim 33, and "the Office dismisses this claim as being
'rejected for the same reason as presented in Claim 9 above."' (App. Br.
26-27.) The Examiner, however, has cited Best's Figures 3-7 against claim
33. (Ans. 13-14 (citing Best i-fi-f 12, 25, 28-29, and Figs. 3-7).)
We agree with the Examiner that Best's Figures 3-7 teach and suggest
controllers as recited in claim 33. For example, Best's Figure 3 discloses (i)
a shadow copy controller (non-volatile control circuit 137) directly
interfaces with the non-volatile memory (NV /Flash memory array die), and
(ii) a memory controller (DRAM control circuit 129) directly interfaces with
the volatile memory (DRAM memory array die) and indirectly inteifaces
with the non-volatile memory (NV /Flash memory array die) through the
shadow copy controller (non-volatile control circuit 137). (See Best, Fig. 3.)
Best's memory controller thus enables a "systematic write-back from the
DRAM [volatile memory] to a Flash memory [non-volatile memory] to
provide a non-volatile image of the DRAM contents." (Ans. 14 (citing
Best i-f 12).)
As Appellant's arguments have not persuaded us of error in the
Examiner's rejection of claim 33, we sustain the Examiner's§ 103(a)
rejection of claim 33 and claim 34, for which Appellant provides the same
arguments. (App. Br. 27 .)
DECISION
The Examiner's rejection of claim 32 under 35 U.S.C. § 112(a) or
35 U.S.C. § 112 (pre-AIA), first paragraph, is reversed.
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The Examiner's rejection of claims 1-3, 5-9, 11-31, 33, and 34 under
35 U.S.C. § 103(a) is affirmed.
The Examiner's rejection of claim 32 under 35 U.S.C. § 103(a) is
reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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