Ex Parte Christensen et al

Board of Patent Appeals and Interferences

Apr 8, 2010

11044567 (B.P.A.I. Apr. 8, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte BJORN PETER CHRISTENSEN,
PETER JUERGEN KLIM,
DUNG QUOC NGUYEN,
and RAYMOND CHEUNG YEUNG
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Appeal 2009-004420
Application 11/044,567
Technology Center 2100
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Decided: April 8, 2010
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Before JAMES D. THOMAS, ST. JOHN COURTENAY III, and
JAMES R. HUGHES, Administrative Patent Judges.

THOMAS, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1 through 20. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.
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Application 11/044,567

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Invention
An apparatus and method for dependency tracking and register file
bypass controls using a scannable register file are provided. With the
apparatus and method, a scannable register file array is provided and used to
track the stage of any instruction in the execution unit. Every entry in the
target vector is updated every cycle to stay synchronized with the
instructions in the execution unit. To keep the register file array
synchronized with the instructions in the execution unit, a right shift of all
the data in each entry of the register file array occurs every cycle. The scan
port of the register file array cells is used as the shift function. (Spec. 31,
Abstract; Fig. 6.)

Representative Claim
1. An apparatus for accessing a register file array in a data
processing system comprising:
a register file array having a plurality of cells; and
a shift clock steering circuit coupled to the register file array,
wherein the shift clock steering circuit controls shifting of data from
one cell to another cell in the register file array via scan ports of the
plurality of cells such that data is shifted from one cell to another cell
at each clock cycle.

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Application 11/044,567

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Prior Art and Examiner’s Rejections
The Examiner relies on the following references as evidence of
anticipation and unpatentability:
Peng 6,633,971 B2 Oct. 14, 2003

Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits,
1103-05, 1115, 1117, 1120, 1125-27 (Oxford University Press, 4th ed. 1998)
(“Sedra”).

Claims 1 through 3, 8, 11 through 13, and 18 stand rejected under
35 U.S.C. § 102(b) as being anticipated by Peng. This reference is utilized
with Sedra within 35 U.S.C. § 103 to reject claims 4 through 7, 9, 10, 14
through 17, 19, and 20.

Claim Groupings
Based on Appellants’ arguments in the Brief on appeal, Appellants
argue independent claim 1 as representative of the subject matter of
independent claims 1 and 11 on appeal. Within the first stated rejection,
dependent claim 3 is representative of the subject matter of dependent claims
3 and 13, and dependent claim 8 is representative of the subject matter of
dependent claims 8 and 18. No other claims are argued within the first
stated rejection under 35 U.S.C. § 102. As to the rejection of various claims
under 35 U.S.C. § 103, dependent claim 4 is representative of the subject
matter of dependent claims 4 and 14. No other claim is argued within the
second stated rejection.

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Application 11/044,567

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ISSUE
Has the Examiner erred in finding that Peng teaches the wherein
clause of representative independent claim 1 on appeal?

FINDINGS OF FACT
1. Peng’s patent relates to a pipeline processor. Within this
patent, the term “data” is inclusive of data and instructions as indicated at
column 1, lines 43 through 45. These types of processors are further
explained in this manner:
The goal of pipeline processors is to execute multiple
instructions per cycle (IPC). Due to pipeline hazards, actual
throughput is reduced. Pipeline hazards include structural hazards,
data hazards, and control hazards. Structural hazards arise when more
than one instruction in the pipeline requires a particular hardware
resource at the same time (e.g., two execution units requiring access to
a single ALU resource in the same clock cycle).

(Col. 1, ll. 59-66.)
Peng’s processor 101 in Figures 1 and 2 includes a CPU core 201 in
Figure 2, the details of which are further shown in Figure 3. This Figure
includes an instruction flow unit 303 that is detailed in Figure 4. Figure 4
includes a register file 407 and pipefile 409 in addition to a pipeline control
unit 401 that includes a pipeline snapshot file, the details of which are
illustrated in Figure 7A-B. Based on the discussion of Figure 4 at columns 5
and 6, the operand file unit comprises register files 407 and pipefile 409.
The IFU 303 reads operands from the register file 407 and then sends the
decoded instructions and the operands to the execution units for processing.
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On the other hand, pipefile 409 operates to collect results from these
execution units and writes them back to the register file 407.
In this regard, the discussion at column 6, lines 45 through 59 is also
instructive:
The operand file unit implements the architecturally defined
general purpose register file 407. In addition, it also implements a
limited version of a reorder buffer called “pipe file” 409 for storing
and forwarding interim results that are yet to be committed to
architectural registers. Because CPU core 201 is principally directed
at in-order execution, there is only a small window of time that
execution results may be produced out-of-order. The present
invention takes advantage of this property and implements a
simplified version of the reorder buffer that allows interim results to
be forwarded as soon as they are produced, while avoiding the
expensive tag passing/matching mechanism usually associated with a
reorder buffer. The operand file implements the data path portion of
this pipe file. The control is implemented in the pipe control unit 401.

Significant teachings relating to the pipe control unit 401 in Figure 4
are revealed here:
The pipe control unit 401 performs a number of operations in
handling the instruction flow. An important feature of the pipe
control unit 401 is the pipeline snapshot file 415 (shown in FIG. 4)
implemented within pipe control unit 401. Snapshot file 415 may be
implemented as a lookup table having a table entry 701 (shown in
FIG. 7) corresponding to each execution stage in the pipeline. The
snapshot file 415 provides a central resource for all pipeline control
operations such as dependency checks, operand forwarding, exception
handling, and the like. In a particular implementation, snapshot file
415 includes four entries corresponding to the three execution pipeline
stages and the write back pipeline stage.

FIG. 7A and FIG. 7B show exemplary snapshot files 701 and
702 indicating entries holding metadata describing the instruction
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execution state at the corresponding pipe stage. As instructions move
from one stage to another, their associated snapshot entry moves to
the corresponding snapshot entry 701 or 702. The contents of each
snapshot entry 701 may be varied to meet the needs of a particular
application.

(Col. 7, ll. 24-42.)
Additionally, column 8, lines 41 through 43 are significant for this
appeal:
Under normal conditions once an instruction has been issued to
an execution unit its entry will progress through each stage of the
snapshot file on each clock edge.

Columns 9 through 11 discuss in detail the operand multiplexers in
Figure 8 and the internal operand forwarding and executing stages in Figure
9. From the illustrations in these two figures alone, a person of ordinary
skill in the art would appreciate the data shifting network among the various
registers consistent with the pipeline flow of Figure 5 and consistent with the
earlier-noted teachings regarding clock cycle processing reproduced in this
Finding of Fact.
Lastly, the discussion at column 11, lines 27 through 38 reveals that
the pipefile 409 in Figure 4 is implemented using traditional CMOS static
random access memory (SRAM) technology.
2. Pages 1103 through 1105 of Sedra teach clocked shift register
arrangements, based upon so-called D flip-flop circuits which are taught at
page 1104 to be edge-triggered. Figure 13.44 and the discussion at page
1104 indicate that clock circuits traditionally have inverted and non-inverted
outputs which are separately used for shift register functions within these
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connected flip-flops. These are characterized as two-phase nonoverlapping
clocks. Figure 13.45 illustrates a master-slave D flip-flop circuit.
(Specification page 14 indicates this type of flip flop is used to comprise the
scan path of the disclosed shift registers comprising the register file array
460.) Significantly, page 1117 illustrates a CMOS SRAM memory cell,
whereas the discussion at pages 1125 and 1126, including the showing in
Figure 13.60, indicate that these SRAMs utilize differential sense amplifiers
for a selected cell that rely upon the inverted and non-inverted clock signals,
discussed earlier in this reference.

PRINCIPLES OF LAW
Anticipation
“A claim is anticipated only if each and every element as set forth in
the claim is found, either expressly or inherently described, in a single prior
art reference.” Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d
628, 631 (Fed. Cir. 1987). Analysis of whether a claim is patentable over
the prior art under 35 U.S.C. § 102 begins with a determination of the scope
of the claim. We determine the scope of the claims in patent applications
not solely on the basis of the claim language, but upon giving claims their
broadest reasonable construction in light of the specification as it would be
interpreted by one of ordinary skill in the art. In re Am. Acad. of Sci. Tech
Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). The properly interpreted claim
must then be compared with the prior art.

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Obviousness
“The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).

ANALYSIS
We refer to, rely upon, and adopt the Examiner’s findings and
conclusions set forth in a rather lengthy manner in the Answer with respect
to the discussion of both references relied upon. Our discussion here will be
limited to the following points of emphasis.
From a person of ordinary skill in the art’s perspective, our Finding of
Fact 1 demonstrates the correctness of the Examiner’s position that Peng
anticipates a shift clock steering circuit that performs shifting functions from
one cell to another in a register file array by means of scanning ports so that
the shifting from one cell to another occurs within or at each clock cycle.
Thus, the arguments presented by Appellants at length in the Brief relating
to the wherein clause of this claim are not persuasive of patentability of
representative independent claim 1 on appeal.
To the extent Appellants argue the lack of so-called scan ports,
including scan in ports and scan out ports, from an artisan’s perspective
these labeled ports reveal no hardware distinction over the input and output
nodes depicted and discussed in the noted figures and text referenced in
Finding of Fact 1. Therefore, we see no patentable distinction by the mere
use of the term “scan port” in any manner among representative independent
claim 1 and representative dependent claim 3. We reach a similar
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conclusion for the use of the term “scan chain” utilizing scan output ports
and scan input ports of respective cells in representative dependent claim 8.
Additionally, Appellants’ admitted prior art Figures 2A-B indicate that
comparable scan in/scan out ports (write/read ports) were known in the art.
With respect to Appellants’ arguments directed at representative
dependent claim 4, we need only address the argument of the lack of proper
combinability within 35 U.S.C. § 103 beginning at page 16 of the Brief. The
fact that column 11 of Peng actually teaches that the noted register discussed
at length in our Finding of Fact 1 is comprised of traditionally known and
typically implemented CMOS static random access memory (SRAM)
technology dovetails very nicely with the teachings of Sedra cited by the
Examiner as we have detailed at length in Finding of Fact 2. Therefore,
using the guidance provided by the earlier-noted case law, the combinability
of the respective teachings of both references would have been obvious to a
person of ordinary skill in the art. This reference combination renders
obvious the disputed feature of dependent claim 4 to the extent recited in the
claim – specifically, that it was known in the shift register/memory circuit
art that data may be shifted from cell to cell utilizing the claimed two clock
signals.
Lastly, no Reply Brief has been filed to contest the Examiner’s
responsive arguments in the Answer.

CONCLUSION AND DECISION
Appellants have not shown that the Examiner erred in finding that
Peng teaches the wherein clause of representative independent claim 1 on
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appeal. Additionally, we find no error in the Examiner’s findings that
representative dependent claims 3 and 8 are also anticipated by Peng.
Lastly, Appellants also have not convinced us of any error in the Examiner’s
position that the subject matter of dependent claim 4 would have been
obvious within 35 U.S.C. § 103 based upon the properly combinable
teachings of Peng and Sedra. Therefore, we affirm the rejection of various
claims on appeal under 35 U.S.C. §§ 102 and 103. All claims on appeal are
unpatentable.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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