13335872 (P.T.A.B. Dec. 21, 2018)

Ex Parte CHOQUETTE et al

Patent Trial and Appeal BoardDec 21, 2018

13335872 (P.T.A.B. Dec. 21, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/335,872 12/22/2011 102324 7590 12/26/2018 Artegis Law Group, LLP/NVIDIA 7710 Cherry Park Drive Suite T #104 Houston, TX 77095 FIRST NAMED INVENTOR Jack Hilaire CHOQUETTE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. NVDA/SC-11-0064-US 1 5142 EXAMINER PETRANEK, JACOB ANDREW ART UNIT PAPER NUMBER 2183 NOTIFICATION DATE DELIVERY MODE 12/26/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): kcruz@artegislaw.com ALGdocketing@artegislaw.com j matthews @artegislaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JACK HILAIRE CHOQUETTE, ROBERT J. STOLL, OLIVIER GIROUX, MICHAEL FETTERMAN, SHIRISH GADRE, ROBERT STEVEN GLANVILLE, and ALEXANDRE JOLY Appeal2018-005282 Application 13/335,872 1 Technology Center 2100 Before DEBRA K. STEPHENS, DANIEL J. GALLIGAN, and DAVID J. CUTITTA II, Administrative Patent Judges. STEPHENS, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. Â§ 134(a) from a final rejection of claims 1-7 and 14--31, which are all of the claims pending in the application. We have jurisdiction under 35 U.S.C. Â§ 6(b). Claims 8-13 have been cancelled. We AFFIRM. 1 According to Appellants, the real party in interest is NVIDIA Corporation (App. Br. 3). Appeal2018-005282 Application 13/335,872 CLAIMED SUBJECT MATTER According to Appellants, the claims are directed to multi-core processor instruction scheduling using pre-decode data (Abstract). Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A method for scheduling instructions without instruction decode, the method comprising: fetching a plurality of instructions corresponding to two or more thread groups from an instruction cache unit, wherein each thread group includes one or more threads; storing the plurality of instructions in a buffer without decoding the plurality of instructions; receiving a separate instruction that includes an opcode and pre-decode data, wherein the opcode is decodable by a processor, and the pre-decode data includes a plurality of multi- bit portions, and each instruction in the plurality of instructions corresponds to a different multi-bit portion of the pre-decode data; selecting an instruction from the plurality of instructions for execution by a processing unit based at least in part on the multi-bit portion of the pre-decode data corresponding to the instruction; decoding the instruction; and dispatching the instruction to the processmg unit for execution. REFERENCES The prior art relied upon by the Examiner in rejecting the claims on appeal is: Kailas Suggs Jiao US 2004/0117597 Al US 2008/0256338 Al US 2010/0201703 Al 2 June 17, 2004 Oct. 16, 2008 Aug. 12, 2010 Appeal2018-005282 Application 13/335,872 Mark Gebhart et al., Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors, 38th International Symposium on Computer Architecture (June 4--8, 2011) (hereinafter "Gebhart"). REJECTIONS Claims 1-7 and 14--31 are provisionally rejected for obviousness-type double patenting based on claims 1-20 of U.S. Patent Application No. 13/333,879, Gebhart, Kailas, and Suggs (Final Act. 2--4). Claims 1-7 and 14--31 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Gebhart, Kailas, and Suggs (id. at 4--15). Claims 1-7 and 14--31 stand rejected under 35 U.S.C. Â§ 103(a) as being unpatentable over Gebhart, Jiao, and Suggs (id. at 16-27). Our review in this appeal is limited only to the above rejections and the issues raised by Appellants. Arguments not made are waived. See MPEP Â§ 1205.02; 37 C.F.R. Â§Â§ 4I.37(c)(l)(iv) and 4I.39(a)(l). ANALYSIS Obviousness-type Double Patenting In the Final Action, the Examiner provisionally rejected claims 1-7 and 14--31 for obviousness-type double patenting based on claims 1-20 of U.S. Patent Application No. 13/333,879 ("the '879 application") (Final Act. 2--4). The '879 application has since issued as US 9,798,548 B2. Because the scope of the claims in the issued patent may be different than the claims in the application used in the provisional obviousness-type double patenting rejection, we decline to reach the merits of the rejection. Should Appellants choose to continue prosecution, we leave it to the Examiner to determine the propriety of the rejection (Ex parte Jerg, 2012 WL 1375142, 3 Appeal2018-005282 Application 13/335,872 *3 (BP AI 2012) (informative) ("Panels have the flexibility to reach or not reach provisional obviousness-type double-patenting rejections.")). 35 U.S.C. Â§ 103(a) As an initial matter, we note that the Examiner rejects claims 1-7 and 14--31 under 35 U.S.C. Â§ 103(a) as being unpatentable over Gebhart, Kailas, and Suggs (Final Act. 4--15) and further rejects claims 1-7 and 14--31 under 35 U.S.C. Â§ 103(a) as being unpatentable over Gebhart, Jiao, and Suggs (id. at 16-27). The Examiner relies on Suggs for similar teachings and reasons in both rejections and Appellants' arguments are directed to Suggs. As such, our discussion of Suggs is dispositive for both rejections. Appellants contend the Examiner erred in finding Suggs teaches "receiving a separate instruction that includes an opcode and pre-decode data, wherein the opcode is decodable by a processor," as recited in claim 1 and similarly recited in claims 14 and 21 (App. Br. 11-14; Reply Br. 3-5). Specifically, Appellants argue because the Examiner maps the claimed pre- decode data to Suggs' pre-decode field, Suggs would have to disclose the recited separate instruction (App. Br. 11 ). Appellants argue Suggs' "pre- decode field ... cannot ... be considered an instruction" (id. at 12; Reply Br. 3). Appellants also argue "Suggs simply discloses a single 16-bit pre- decode field in a cache line that indicates the length of the different instructions in the instruction field of that same cache line" but "the 16-bit pre-decode field is not part of some separate instruction" (App. Br. 11-12). We are not persuaded. The Examiner finds, and we agree, Suggs' "pre[-]decode bits associated with each instruction in a L 1 cache line" (Final Act. 6 (citing Suggs ,r,r 47, 53, 57, Fig. 5)) teaches "receiving a separate 4 Appeal2018-005282 Application 13/335,872 instruction that includes an opcode and pre-decode data, wherein the opcode is decodable by a processor." In particular, we understand that the Examiner relies on Suggs for "inserting pre[-]decoding bits for variable-length instructions of a cache line to detect instruction boundaries" (see Final Act. 28; see also Suggs ,r 53 ("[I]n variable length instruction set architectures ... instruction boundaries are variable .... Pre[-]decode information ... may be saved to indicate where instruction boundaries occur.")). Appellants' argument that Suggs' "pre-decode field ... cannot also be considered an instruction" (App. Br. 12-14; Reply Br. 3-5), i.e., Suggs' pre- decode field does not teach "a separate instruction," does not address the Examiner's finding that "each instruction in a LI cache line" teaches "a separate instruction" (Final Act. 6 (citing Suggs ,r,r 47, 53, Fig. 5)). As Appellants point out (App. Br. 11-12), in the Examiner's relied-upon portions of Suggs, Suggs discloses "a cache line storing sixteen instruction bytes, each line ... includes a 128-bit instruction field 422 [and] a 16-bit pre[-]decode field 424" (Suggs ,r 47, Fig. 5). The "instruction field 422 stores sixteen instruction bytes ... correspond[ing] to two or more instructions, depending on the lengths of the instructions in the fetch window" (id.). And the "[p ]re[-]decode information ... indicate[ s] where instruction boundaries occur" within instruction field 422 (id. ,r 53; see id. ,r 48). As such, Suggs' cache line includes multiple instructions, having "separate" boundaries, within instruction field 422. Further, contrary to Appellants' argument that Suggs' "pre-decode field is not part of some separate instruction" (App. Br. 11-12), the instructions in the cache line "include[]" respective "pre-decode data" field 5 Appeal2018-005282 Application 13/335,872 424 indicating respective instruction boundaries (Suggs ,r 47, 53; see id. i1 48). Appellants' additional arguments that "Examiner's use of Official Notice is improper" (App. Br. 14--15) and that the Examiner engages in "impermissible hindsight" (id. at 15) are also unavailing. Appellants' October 30, 2017 Petition regarding the Examiner's use of Official Notice was denied by the Commissioner for Patents because Appellants did not properly traverse the Examiner's Official Notice (February 20, 2018 Decision on Petition 4). Moreover, Appellants' argument is based on whether "pre-decode data is stored in a cache line as a separate instruction" (App. Br. 14); however, as discussed above, Suggs' cache line instruction field teaches "separate instruction[ s]." Moreover, Appellants have not persuaded us the Examiner relies on improper hindsight to make "the legal conclusion" that it would have been obvious to receive "a separate instruction that includes an opcode and pre- decode data, where the opcode is decodable by a processor" (id. at 15 ( emphasis omitted)). Rather, the Examiner finds that Suggs teaches that disputed limitation, as discussed above. Accordingly, we are not persuaded by Appellants' contention. Accordingly, we are not persuaded the Examiner fails to show Suggs teaches or suggests "receiving a separate instruction that includes an opcode and pre-decode data, wherein the opcode is decodable by a processor," as recited in claim 1 and similarly recited in claims 14 and 21. Nor are we persuaded the limitation as recited in claims 1, 14, and 21 would not have been obvious over the combined references, to an ordinarily skilled artisan at the time of the invention. Therefore, we sustain the rejection of independent 6 Appeal2018-005282 Application 13/335,872 claims 1, 14, and 21 under 35 U.S.C. Â§ 103(a) as being unpatentable over Gebhart, Kailas, and Suggs and the rejection of independent claims 1, 14, and 21 under 35 U.S.C. Â§ 103(a) as being unpatentable over Gebhart, Jiao, and Suggs. We likewise sustain the Examiner's rejections of dependent claims 2-7, 15-20, and 22-31 under 35 U.S.C. Â§ 103(a) because Appellants offer no additional persuasive arguments for patentability (see App. Br. 16). DECISION The Examiner's rejection of claims 1-7 and 14--31 under 35 U.S.C. Â§ 103(a) as being unpatentable over Gebhart, Kailas, and Suggs is affirmed. The Examiner's rejection of claims 1-7 and 14--31 under 35 U.S.C. Â§ 103(a) as being unpatentable over Gebhart, Jiao, and Suggs is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. Â§ 1.136(a). See 37 C.F.R. Â§ 4I.50(f). AFFIRMED 7