Ex Parte CHOI et al

Patent Trial and Appeal Board

Jul 3, 2018

14872285 (P.T.A.B. Jul. 3, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/872,285 10/01/2015
30593 7590 07/06/2018
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON, VA 20195
FIRST NAMED INVENTOR
MinhoCHOI
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
8947-000939-US 1943
EXAMINER
TRA, ANH QUAN
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
07/06/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
dcmailroom@hdp.com
pshaddin@hdp.com
jcastellano@hdp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MINHO CHOI, YUS KO, DONGJIN KEUM,
HWA YEAL YU, and YOUNGHOON LEE
Appeal2017-008937
Application 14/872,285
Technology Center 2800
Before CATHERINE Q. TIMM, N. WHITNEY WILSON, and
SHELDON M. McGEE, Administrative Patent Judges.
McGEE, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellants 1 seek our review of the
Examiner's rejections of claims 1-10 and 34.
We have jurisdiction. 35 U.S.C. § 6.
We affirm.
SUBJECT MATTER
The subject matter on appeal relates to an electronic device containing
a power management integrated circuit (PMIC). Spec. i-f 2.
Sole independent claim 1 is illustrative of the claimed subject matter
and is copied below:
1 The real party in interest is identified as Samsung Electronics Co., Ltd.
App. Br. 4.
Appeal2017-008937
Application 14/872,285
1. An electronic device comprising:
a power management integrated circuit (PMIC) including a
plurality of regulators, each of the plurality of regulators
having a current meter configured to measure a respective
load current; and
a load device configured to receive real-time load current
information from the PMIC and to perform a performance
improvement operation based on the real-time load current
information.
App. Br. 22.
The Examiner rejects claims 1, 2, and 10 under 35 U.S.C. § 102(a)(l)
as anticipated by Oh. 2 Final 2-3. The Examiner additionally rejects claims
3-9 and 34 under 35 U.S.C. § 103(a) as unpatentable over Oh combined
with the teachings of J ayaraj 3 (claims 3 and 4 ), Rader4 (claim 5), Schultz5
(claims 6-9 and 34 ). Final 3-5.
STATEMENT OF THE CASE
In rejecting sole independent claim 1, the Examiner finds that Oh
discloses the recited electronic device. Final 2. Specifically, the Examiner
maps Oh's element 10, illustrated in Figure 3, to the claimed "PMIC", Oh's
DC/DC converters 1101 and 1102 and current detectors 1301 and 1302 to the
claimed "regulators" and "current meters," respectively. Id. The Examiner
further maps Oh's CPU 20 and an un-illustrated circuit to the recited "load
device". Id. The Examiner finds that Oh's element 20 is "configured to"
2 US 2010/0219687 Al, published September 2, 2010.
3 US 2014/0347028 Al, published November 27, 2014.
4 US 2014/0266123 Al, published September 18, 2014.
5 US 2011/0105867 Al, published May 5, 2011.
2
Appeal2017-008937
Application 14/872,285
carry out the recited functions of the claimed "load device," i.e., 1) "receive
real-time load current information from the PMIC and [2)] to perform a
performance improvement operation based on" such information. Id.
Oh's Figure 3 is provided below:
~FlG-. 3
Main Power fri ---------------------·'\
(3.7Wle:l:tiomA) r-·2_:~~--~~. ------- 1.,,0 I
~T110,:oc~.-~ ,~, I ~sef~,,
t-~m,,.,..,I OCiOC Conv~dm 2 ! rnH '"~' , ,..w,,L."'""'Q.9Q2. . . "'
I ~ ... -................. l 2 ·· · I I {3.3.ViH)OQmA)
: ~ ~)("'.("(~.
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