Ex Parte Cheng et al

Patent Trial and Appeal Board

Mar 12, 2014

12055128 (P.T.A.B. Mar. 12, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte MICHAEL CHENG and RANDY EUGENE FOX1
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Appeal 2011-007855
Application 12/055,128
Technology Center 2400
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Before JEAN R. HOMERE, MICHAEL J. STRAUSS, and
LARRY J. HUME, Administrative Patent Judges.

HUME, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 The Real Party in Interest is International Business Machines Corporation.
App. Br. 1.
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STATEMENT OF THE CASE2
The Invention
Appellants’ “invention generally relates to the field of computer
software, and particularly to a method to provide interoperability of different
version protocols.” Spec. ¶ [0002] (“FIELD OF THE INVENTION”).
Exemplary Claims
Claims 1 and 7, reproduced below, are representative of the subject
matter on appeal (emphases added):
1. A method of preserving interoperability between a
first process with a first protocol and a second process with a
second protocol wherein the second process receives the data
from the first process, comprising:
receiving data from the first process;
utilizing the first protocol to de-serialize the data;
converting the data into an in-memory representation of
the first protocol format; and
transforming the in-memory presentation of the first
protocol format to an in-memory representation of the second
protocol format, the transforming being performed in a JAVA
environment, said transforming using reflection to call methods
to convert between a first set of classes and a second set of
classes, the second set of classes being an upgraded set of
classes relative to the first set of classes, wherein the second
protocol is an upgraded version of the first protocol and the

2 Our decision refers to Appellants’ Appeal Brief (“App. Br.,” filed
Nov. 15, 2010); Reply Brief (“Reply Br.,” filed Mar. 31, 2011); Examiner’s
Answer (“Ans.,” mailed Feb. 1, 2011); Final Office Action (“FOA,” mailed
Apr. 15, 2010); and the original Specification (“Spec.,” filed Mar. 25, 2008).
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second process is capable of processing both the second
protocol and the first protocol.
7. A method for preserving interoperability between a
first process with a first protocol and a second process with a
second protocol wherein the second process sends data to the
first process, comprising:
transforming an in-memory representation of data from a
second data format to a first data format, the transforming
being performed in a JAVA environment, said transforming
using reflection to call methods to convert between a second set
of classes and a first set of classes, the second set of classes
being an upgraded set of classes relative to the first set of
classes;
serializing the data through the first protocol; and
converting the in-memory representation of the first data
format into a data suitable for being understood by the first
protocol, wherein the second protocol is an upgraded version of
the first protocol and the second process is capable of
processing the second data format and the first data format.
Prior Art
The Examiner relies upon the following prior art in rejecting the
claims on appeal:
Bunton US 7,010,607 B1 Mar. 7, 2006
Kawaguchi US 7,373,632 B1 May 13, 2008
Rejection on Appeal
Claims 1-20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Bunton and Kawaguchi. Ans. 3.
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ISSUES
Appellants argue (App. Br. 5-12; Reply Br. 4-7) the Examiner’s
rejection of claims 1-20 under 35 U.S.C. § 103(a) as being unpatentable over
the combination of Bunton and Kawaguchi is in error. These contentions
present us with the following issues:
(a) Did the Examiner err in finding that the cited prior art
combination teaches or suggests all the limitations recited in claims 1 and 7?
(b) Did the Examiner err in finding the combination of Bunton and
Kawaguchi teaches or suggests the use of bit manipulation with object
oriented programming concepts and therefore “violates the understood
separation between the application layer and the link layer” (App. Br. 5)?
FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Bunton
FF1. Bunton teaches or suggests “[l]ogic on the receiving chip de-
serializes and de-codes the ten bit streams, which are converted to the eight
byte wide flit [(flow control digit)] data stream for next higher layer.” Col.
28, ll. 39-42.
FF2. Bunton teaches or suggests receiving IPv4 packets and
converting them to IPv6 packets. Col. 43, ll. 3-39.
FF3. Burton teaches or suggests storing IPv4 data until later
conversion into IPv6 format. Col. 42, ll. 17-39, and col. 43, ll. 21-39.
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FF4. Bunton teaches or suggests backward compatibility between
newer and older protocol versions. Col. 47, Table 9 and ll. 15-48.
FF5. Bunton also teaches or suggests serializing bits into a data
stream. Col. 28, ll. 35-38.
Kawaguchi
FF6. Kawaguchi teaches or suggests transforming an in-memory
representation of a first protocol format to an in-memory representation of a
second protocol format using the Java Reflection API for class conversion,
where the second protocol format is an upgraded version of the first protocol
format. Col. 1, ll. 4-53 and col. 2, ll. 40-63.
ANALYSIS
We only consider those arguments actually made by Appellants in
reaching this decision, and we do not consider arguments which Appellants
could have made but chose not to make in the Briefs so that any such
arguments are deemed to be waived. 37 C.F.R. § 41.37(c)(1)(vii).
We disagree with Appellants’ conclusions with respect to claims 1
and 7, and we adopt as our own (1) the findings and reasons set forth by the
Examiner in the action from which this appeal is taken and (2) the reasons
and rebuttals set forth by the Examiner in the Examiner’s Answer in
response to Appellants’ Arguments. However, we highlight and address
specific findings and arguments regarding claim 1 for emphasis as follows.
Issue 1(a)
Appellants contend the Examiner’s rejections “violate the network
stack,” and “[c]learly, Bunton does not disclose receiver logic, which
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implements the Link Encoding layer, converting endnode addresses that are
not visible until the Transport or Network layers.” App. Br. 7. We disagree
with Appellants’ arguments, which are not commensurate with the scope of
claim 1 because the claim does not recite “the network stack”, or the
visibility of endnode addresses in different layers.
Appellants further contend the Examiner “erroneously interprets the
encapsulation of a 48 bit address into a 64 bit address as converting de-
serialized data into an in-memory representation of the first protocol format”
(id.), and also contends error in reliance upon “the same ‘conversion’ of a 48
bit address into a 64 bit address for [teaching ‘transforming an in-memory
representation of the de-serialized data from the first protocol format into a
second protocol format’].” Id.
In response, the Examiner finds, and we agree, “[u]tilizing a protocol
in this context can reasonably be interpreted as maintaining the same data
format protocol or addressing protocol during the de-serialization or
serialization process . . . [and, clearly,] Bunton does this as Bunton discloses
that the data received is later converted from Ipv4 to [Ipv6].” Ans. 8; and
see FF1 and FF2, supra. We find the recited “converting the data into an in-
memory representation of the first protocol format” may reasonably be
construed as storing the received IPv4 data in a memory, as taught by
Bunton. See FF3.
We also find Appellants have mischaracterized the Examiner’s
rejection with respect to the purported equation of the first protocol with
Bunton’s conversion occurring during serialization/deserialization from/to 8
byte words and 10 byte words. App. Br. 6. The Examiner has instead
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equated IPv4 with the first protocol format and IPv6 with the second
protocol format, a correspondence with which we agree. Ans. 10.
During examination, a claim must be given its broadest reasonable
interpretation consistent with the specification, as would be interpreted by
one of ordinary skill in the art. Because the applicant has the opportunity to
amend claims during prosecution, giving a claim its broadest reasonable
interpretation will reduce the possibility that the claim, once issued, will be
interpreted more broadly than is justified. In re Yamamoto, 740 F.2d 1569,
1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989)
(“During patent examination the pending claims must be interpreted as
broadly as their terms reasonably allow.”).
We note Appellants’ Specification states, inter alia, “[d]uring
serialization, the in-memory representation of the un-upgraded format data
may be converted into a proper data structure for the first protocol. The
converted data may be sent to the first process. As such, the interoperability
of the first process may be preserved.” Spec. ¶ [0008] (emphasis added).
First, we find the portion of the Specification cited above discloses the
received IPv4 data is stored in a memory, i.e., as an “in-memory
representation.” Second, the permissive nature of Appellants’ disclosure,
i.e., use of the phrase “may be,” does not preclude mere storage of the data
in the first protocol format as found by the Examiner (Ans. 8), and also does
not require any “conversion,” at least at that stage of the process. We find
received IPv4 data would already be in a “proper data structure for the first
[IPv4] protocol.”
Thus, we find no error in the Examiner’s claim construction analysis.
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Issue 1(b)
Appellants argue the combination of Bunton and Kawaguchi “is
inappropriate . . . because it suggests disclosure of bit manipulation should
be combined with disclosure of object oriented programming concepts.”
App. Br. 8. In particular, Appellants contend “[t]he Examiner also lacks any
support to argue that manipulating bit streams at the link encoding layer
would facilitate isomorphic interfacing or provide proxies without common
shared libraries” because “[t]he JAVA environment exists at the application
layer, and not down in the link encoding layer, transport layer or network
layer.” Id. In response, the Examiner finds:
Clearly object-oriented software is nothing novel or non-
obvious, dating back to the 1980’s and prior. One of ordinary
skill in the art at the time Appellant’s invention was made
would have understood that Bunton’s disclosed FIO transport
and network layer software implementation could have been
coded using object-oriented language tools and methods such as
the Java Reflection API [as taught by Kawaguchi].
Ans. 12. We agree with the Examiner because we find there to be nothing
new and nonobvious by the use of object oriented software development,
including a Java implementation approach. See FF6. Appellants have
provided no evidence that combining such teachings was “uniquely
challenging or difficult for one of ordinary skill in the art,” Leapfrog
Enterprises, Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007),
nor have Appellants presented evidence that this incorporation yielded more
than expected results.
Rather, we find that Appellants’ invention is simply a combination of
known teachings that realize a predictable result. The Supreme Court has
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determined the conclusion of obviousness can be based on the interrelated
teachings of multiple patents, the effects of demands known to the design
community or present in the marketplace, and the background knowledge
possessed by a person having ordinary skill in the art. KSR Int’l Co. v.
Teleflex, Inc., 550 U.S. 398, 418 (2007). The skilled artisan would “be able
to fit the teachings of multiple patents together like pieces of a puzzle” since
the skilled artisan is “a person of ordinary creativity, not an automaton.” Id.
at 420-21.
Accordingly, we find no error in the Examiner’s finding that the
combination of Bunton and Kawaguchi would have at least suggested the
recited “transforming” step of claim 1.
Independent Claim 7
As for independent claim 7, Appellants’ arguments are the same as for
claim 1 (App. Br. 9-10), but add an additional contention, as follows:
The totality of the assertions by the Examiner are not only
unsupported by Bunton but conflict with Bunton and the use of
the 64 bit GUID . . . [because i]f a 64 bit GUID is being used to
address an endnode, then the intermediate nodes will use the 64
bit GUID. Converting the 64 bit GUID back into a 48 bit
GUID restores the risk of the endnode address not being
unique.
App. Br. 11.
In response, the Examiner finds, “[c]laims 7 and 17 represent the
reverse process to claims 1 and 14. Bunton discloses the backward
compatibility . . . .” Ans. 7. We agree with the Examiner’s finding because
Bunton specifically addresses the issue of backward compatibility with
legacy protocols, as cited. See FF4. Further, as discussed, supra, we find
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Appellants have misconstrued the Examiner’s findings concerning which
portion of the reference combination was being relied upon for teaching or
suggesting the first protocol, and which portion for the second protocol.
App. Br. 6; and see Ans. 10.
Appellants further argue, “Bunton does not disclose transmitter logic,
which implements the Link Encoding layer, converting endnode addresses
that are not visible until the Transport or Network layers.” App. Br. 10. We
find Appellants’ arguments are not commensurate with the scope of claim 7,
as claim 7 does not recite features relied upon in Appellants’ arguments.
Accordingly, based upon the findings above, on this record,
Appellants have not provided sufficient evidence or argument to persuade us
of any reversible error in the Examiner’s reading of the contested limitations
on the cited prior art combination, nor do we find error in the Examiner’s
resulting legal conclusion of obviousness. Therefore, we sustain the
Examiner’s obviousness rejection of independent claims 1 and 7. As
Appellants have not provided separate arguments with respect to
independent claims 14 and 17, or dependent claims 2-6, 8-13, 15, 16, and
18-20, rejected on the same basis as claims 1 and 7, we similarly sustain the
Examiner’s rejection of these claims under 35 U.S.C. § 103(a).
CONCLUSIONS
The Examiner did not err with respect to the unpatentability rejection
of claims 1-20 under 35 U.S.C. § 103(a) over the cited prior art combination,
and we sustain the rejection.

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DECISION
We affirm the Examiner’s decision rejecting claims 1-20.
AFFIRMED

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