Ex Parte Chen et al

Patent Trial and Appeal Board

Oct 22, 2018

12731623 (P.T.A.B. Oct. 22, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/731,623 03/25/2010
115309 7590 10/24/2018
W &T/Qualcomm
106 Pinedale Springs Way
Cary, NC 27511
FIRST NAMED INVENTOR
Nan Chen
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
071709/1173-524 1473
EXAMINER
REIDLINGER, RONALD LANCE
ART UNIT PAPER NUMBER
2824
NOTIFICATION DATE DELIVERY MODE
10/24/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@wt-ip.com
us-docketing@qualcomm.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NAN CHEN and RITU CHABA
Appeal 2018-000026
Application 12/731,623
Technology Center 2800
Before CATHERINE Q. TIMM, ROMULO H. DELMENDO and
JENNIFER R. GUPTA, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellants2 appeal from the
Examiner's decision to reject claims 1---6, 9, 10, 12, 20-26, 28, 37--42, 44,
1 In explaining our Decision, we cite to the Specification dated March 25,
2010 (hereinafter "Spec."); Final Office Action dated Jan. 20, 2017
(hereinafter "Final"); Appeal Brief dated April 4, 2017 (hereinafter "Appeal
Br."); Examiner's Answer dated August 4, 2017 (hereinafter "Ans."); and
Reply Brief dated Sept. 29, 2017 (hereinafter "Reply Br.").
2 Appellants identify the real party in interest as Qualcomm Incorporated.
Appeal Br. 1.
Appeal 2018-000026
Application 12/731,623
46, 47, 49, 50, and 53-55 under 35 U.S.C. § 103(a) as obvious over Do3 in
view ofWalters, 4 to reject claims 7 and 50, for which the Examiner
optionally adds AAPA, 5 and to reject claims 11 and 27, for which the
Examiner adds Kim. 6 Final 3-18; Ans. 2-20. We have jurisdiction under
35 U.S.C. § 6(b).
Because the rejections are based on a faulty claim interpretation, we
REVERSE. But based on a corrected interpretation, we enter a NEW
GROUND OF REJECTION.
The claims are directed to an apparatus comprising a current latched
sense amplifier (see, e.g., claims 1 and 20) and a method of amplifying
current (see, e.g., claim 53). In arguing against the rejection of claim 1,
Appellants concentrate on particular language found in that claim. Appeal
Br. 8. We reproduce below claim 1 with the limitations at issue italicized:
1. An apparatus comprising:
a current latched sense amplifier comprising:
a first transistor having a first source coupled to a first
bit line and a first gate configured to receive an input sense
signal, wherein the first transistor is configured to supply a first
initial voltage to a first output node based on a first voltage of
the first bit line when the input sense signal has a first logic
level and to isolate the first output node from the first bit line
when the input sense signal has a second logic level;
a second transistor having a second source coupled to a
second bit line and a second gate configured to receive the
input sense signal, wherein the second transistor is configured
3 Do, US 7,586,803 B2, issued Sept. 8, 2009.
4 Walters, Jr., US 4,804,871, issued Feb. 14, 1989.
5 Appellants' Admitted Prior Art (hereinafter "AAPA"). Spec. ,r,r 2-8.
6 Kim, US 7,372,746 B2, issued May 13, 2008.
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Application 12/731,623
to supply a second initial voltage to a second output node based
on a second voltage of the second bit line when the input sense
signal has the first logic level and to isolate the second output
node from the second bit line when the input sense signal has
the second logic level;
a third transistor coupled to the second transistor and
having a third gate directly coupled to the second bit line, the
third transistor configured to discharge the first output node
when the input sense signal has the second logic level;
a fourth transistor coupled to the first transistor and
having a fourth gate directly coupled to the first bit line, the
fourth transistor configured to discharge the second output node
when the input sense signal has the second logic level; and
a fifth transistor having a fifth gate configured to receive
the input sense signal, the fifth transistor coupled to the third
transistor and to the fourth transistor.
Appeal Br. 35 (claims appendix).
OPINION
In rejecting claims 1---6, 9, 10, 12, 20-26, 28, 37--42, 44, 46, 47, 49,
50, and 53-55 as obvious over Do in view of Walters, the Examiner finds
that Do teaches the transistors required by claim 1, but does not teach that
the first, second, and fifth transistors are configured to receive the same
input sense signal. Final 3-5. Do teaches using two different signals, one
signal (CTR_CGS) that is received by transistors PM13 and PM14 (first and
second transistors of claim 1) and another signal (IOSTP) that is received by
transistor NM 11 ( fifth transistor of claim 1 ). Do Fig. 3. Thus, the Examiner
relies on Walters to support a finding of a suggestion within the prior art for
delivering the same signal to all three transistors. Final 5.
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Application 12/731,623
Appellants do not dispute that the only difference between the
apparatus of Do and that of claim 1 is in the signals received by the first,
second, and fifth transistors. Appeal Br. 6-8. Instead, Appellants contend
that the Examiner's finding of a reason to merge the Do's CTR_CGS and
IOSTP control signals into a single control signal C3 as taught by Walters is
faulty. Compare Final 5, with Appeal Br. 10-29.
The problem is that Do, in fact, has a structure meeting all the
structural limitations of claim 1. This is because claim 1 is not as limited as
assumed by both the Examiner and Appellants.
Claim 1 is directed to an apparatus. An apparatus is defined by its
structural parts. See Burr v. Duryee, 68 U.S. (1 Wall.) 531, 570 (1863) ("A
machine is a concrete thing, consisting of parts, or of certain devices and
combination of devices."). Claim 1 recites a current latched sense amplifier
having five structural parts, i.e., five transistors.
The Examiner and Appellants assume that a prior art structure must
have transistors that, in fact, receive the same input sense signal to meet the
requirements of claim 1. But the prior art need not. The phrases
"configured to receive an input sense signal" and "configured to receive the
input sense signal" in claim 1 are directed to the structure of the gates of the
first, second, and fifth transistors. There is no identified evidence that a gate
"configured to receive an input sense signal" is different in structure from a
gate configured to receive a different signal. Where the signal originates
does not impact the structure of the gate.
There is no dispute that Do teaches first, second, and fifth transistors
that receive signals. Although the fifth transistor receives a different signal
(IOSTP) than the first and second transistors (CTR_CGS), it is reasonable to
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Application 12/731,623
conclude that the signal origin does not distinguish the fifth transistor
structurally from the first and second transistors. Thus, Do, in fact,
anticipates claim 1. Claim 1 does not require any structure carrying the
signals between the various transistors. Reciting that the gates are
configured to receive particular signals does not provide the necessary
structure to differentiate the amplifier of claim 1 from the amplifier of Do.
Thus, we reject claim 1 under 35 U.S.C. §102(e) as anticipated by Do.
All of the Examiner's rejections and Appellants' arguments in this
appeal hinge on an improperly narrow reading of the claims. The Examiner
should re-evaluate the other rejections and determine the patentability of the
other claims based on the claim interpretation advanced above. We are
cognizant of the fact that claims 53-55 are directed to the method, not the
apparatus. However, Appellant did not direct any arguments to the process
steps recited in those claims. See Appeal Br. 30-31. Thus, we do not here
review those claims.
CONCLUSION
We do not sustain the Examiner's rejections, but we enter a new
ground of rejection.
DECISION
The Examiner's decision is reversed and a new ground of rejection of
claim 1 entered under 37 C.F.R. § 4I.50(b).
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Appeal 2018-000026
Application 12/731,623
TIME PERIOD FOR RESPONSE
This decision contains a new ground of rejection pursuant to
37 C.F.R. § 4I.50(b). 37 C.F.R. § 4I.50(b) provides "[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review."
37 C.F.R. § 4I.50(b) also provides that the Appellant, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new ground of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the proceeding
will be remanded to the examiner ....
(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same record ....
REVERSED; 37 C.F.R. § 4I.50(b)
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