Ex Parte Chen et al

Board of Patent Appeals and Interferences

Jun 27, 2012

11637550 (B.P.A.I. Jun. 27, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte SHAO-CHUN CHEN, PATRIC O'NEILL, PETER L. SOTOS,
JEONG M. LIM, and SIDNEY ANDREW JACOBI
____________________

Appeal 2010-003598
Application 11/637,550
Technology Center 2100
____________________

Before LANCE LEONARD BARRY, ST. JOHN COURTENAY III,
and THU A. DANG, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

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I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 36-44 and 46-55 (App. Br. 3). Claims 1-35 have been cancelled
(App. Br. 14). Claims 45 and 56 have been objected to (App. Br. 3). We
have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

A. INVENTION
Appellants’ invention is directed to a system and method of updating
a version of firmware resident in memory; wherein, the device memory is
initialized with a known pattern to greater enable the detection of free
unused memory space (Abstract).

B. ILLUSTRATIVE CLAIM
Claim 36 is exemplary:
Claim 36. A system for updating memory in an
electronic device, the system comprising:

at least one processor that, during operation, executes
generator code for generating a software package from a
plurality of code modules for the electronic device;

layout preprocessor code executable by the at least one
processor for parsing a memory layout specification and that
receives at least one parameter that represents an estimated
probability of future change of one or more code modules, to
produce memory mapping information that assigns to each of
the plurality of code modules space in one of a plurality of
individual portions of the memory, based upon the memory
layout specification;

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wherein execution of the layout preprocessor code
determines an amount of unassigned space in the memory upon
assignment of space in the memory to the plurality of code
modules; and

wherein execution of the generator code locates a
corresponding fraction of the unassigned space in the memory
in each of the individual portions of the memory, in accordance
with the memory mapping information.

C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Matsuda US 5,913,027 Jun. 15, 1999
Britt US 6,230,319 Bl May 08, 2001
Lee US 2001/0052066 Al Dec. 13, 2001
Kravitz US 6,397,385 B1 May 28, 2002
Rajaram US 2003/0023964 Al Jan. 30, 2003

H.M. Deitel & P.J. Deitel, How to Program 147-191 (Prentice
Hall 1994).

Claims 36-42 and 46 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kravitz in view of Rajaram, Britt, and Dietel.
Claims 43 and 44 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kravitz in view of Rajaram, Britt, Dietel, and Lee.
Claims 47-53 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kravitz in view of Rajaram, Britt, Dietel, and Matsuda.
Claims 54 and 55 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kravitz in view of Rajaram, Britt, Dietel, Matsuda, and
Lee.

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II. ISSUE
The dispositive issue before us is whether the Examiner has erred in
finding that the combination of Kravitz, Rajaram, Britt, and Dietel teaches or
would have suggested “[a] system for updating memory in an electronic
device, the system comprising: … layout preprocessor code executable by
the at least one processor for parsing a memory layout specification and that
receives at least one parameter that represents an estimated probability of
future change of one or more code modules” (claim 1, emphasis added).

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Kravitz
1. Kravitz discloses a software upgrade mechanism and method
which includes establishing in the base software architecture a reserved
memory area held for prospective upgrades (col. 2, ll. 41-47).
2. When an upgrade is to be built, a software upgrade mechanism
writes upgrade source files, places them within the file set of an existing
base build files (previously written), and writes the up-grade source files
(col. 2, ll. 48-53).
3. An appropriate make/build software utility receives the base
build files, upgrades source files, and builds instructions; wherein, the build
instructions notify an associated compiler and linker where to locate in
memory the various portions of the build depending upon the names of those
products (col. 2, ll. 58-63). The products of the upgrade source files having
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particular names are located at designated addresses in the reserved memory
area (col. 2, ll. 63-65).
Rajaram
4. Rajaram discloses a compactor that resizes different portions of
the memory block, such that unused areas of the memory are used to make a
memory block section large enough for a new code section (¶ [0070]).
Britt
5. Britt discloses placement of code in a particular section of
memory if it is likely to be upgraded or reconfigured (col. 11, ll. 11-15).
Dietel
6. Dietel discloses the use of parameters as means for providing
communicating information between functions (p. 150, Sect. 5.4).

IV. ANALYSIS
Claims 36-42 and 46
As to independent claim 36, Appellants contend that the “feature [of
‘layout preprocessor code ... that receives at least one parameter that
represents an estimated probability of future change of one or more code
modules’ (claim 36)] is neither shown nor made obvious in … any of the
references of the four-reference combination” (App. Br. 8).
However, the Examiner finds that “Britt teaches memory mapping
information based on a probability of change in terms of code that is
‘considered likely to be upgraded or reconfigured’” (Ans. 12). The
Examiner notes that “[u]pgrading or reconfiguring code is reasonably
regarded as a form of updating” (Ans. 12-13). The Examiner notes further
that “Kravitz is relied upon to disclose ‘[a] system for updating memory in
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an electronic device, the system comprising ... layout preprocessor code’”
(Ans. 13) and “Deitel is relied upon to teach the use of parameters for
communication information between functions” (id.).
Kravitz discloses a software upgrade mechanism and method which
includes establishing in the base software architecture a reserved memory
area for prospective upgrades (FF 1). When an upgrade is to be built, the
software upgrade mechanism (having a processor that executes generator
code) writes upgrade source files, places them within a file set of an existing
base build, and writes the up-grade source files (FF 2). An appropriate
make/build software utility (generator code) receives the base build files,
upgrades source files, and builds instructions (layout preprocessor code) (FF
3).
In addition, Rajaram discloses a compactor that resizes different
portions of the memory block, allotting unused areas for the new code
sections (FF 4). Furthermore, Britt discloses placement of code in a
particular section of memory if it is likely to be upgraded or reconfigured
(FF 5). Moreover, Dietel discloses the use of parameters as means for
providing communicating information between functions (FF 6).
Our reviewing Court has found that:
It is impermissible to use the claimed invention as an
instruction manual or “template” to piece together the teachings
of the prior art so that the claimed invention is rendered
obvious. This court has previously stated that “[o]ne cannot use
hindsight reconstruction to pick and choose among isolated
disclosures in the prior art to deprecate the claimed invention.”

In re Fritch, 972 F.2d 1260, 1266 (Fed. Cir. 1992) (quoting In re
Gorman, 933 F.2d 982, 987 (Fed. Cir. 1991) and In re Fine, 837 F.2d 1071,
1075 (Fed. Cir. 1988)).
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Although the Examiner finds that the combined teachings of Kravitz,
Rajaram, Britt, and Dietel disclose “‘layout preprocessor code’ … ‘build
instructions’” (Ans. 4, emphasis removed) that “receives at least one
parameter that represents an estimated probability of future change of one or
more code modules, to produce memory mapping information” (Ans. 5,
emphasis removed), we find that Kravitz does not disclose that the build
instructions (layout preprocessor code) receive any data at all. Rather, the
make/build software utility (generator code) receives the base build files,
upgrades source files, and builds instructions (FF 3). In agreement with
Appellants, we find that to add, in hindsight, the teaching of placement of
code having a likelihood of being upgraded in a particular section of
memory, as disclosed in Britt, and a parameter, as disclosed in Dietel, with
the build instructions (layout preprocessor code) of Kravitz would not
produce build instructions that receive a parameter representing an estimated
probability of change for a code mode. That is, we find that the combined
teachings of Kravitz, Rajaram, Britt, and Dietel neither teach nor suggest
“[a] system for updating memory in an electronic device, the system
comprising: … layout preprocessor code executable by the at least one
processor … that receives at least one parameter that represents an estimated
probability of future change of one or more code modules” (claim 36).
Accordingly, we find that Appellants have shown that the Examiner
erred in rejecting claim 36 under 35 U.S.C. § 103(a) over Kravitz in view of
Rajaram, Britt, and Dietel. Similarly, claims 37-42 and 46 (depending from
claim 36) which have not been argued separately stand with claim 36.
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Claims 43, 44, 47-53, 54, and 55
As to independent claim 47 having similar claim language to that of
claim 36, Appellants provide a similar argument to that of claim 36 (App.
Br. 10-11). As to dependent claims 43, 44, 54, and 55, Appellants argue that
claims 43 and 44 are patentable over the cited prior art for the same reasons
asserted with respect to claim 36 (App. Br. 9) and that claims 54 and 55 are
patentable over the cited prior art for the same reasons asserted with respect
to claim 47 (App. Br. 12).
As noted supra, we reversed the rejection of claim 36. The Examiner
has not identified how Matsuda cures the noted deficiencies of Kravitz,
Rajaram, Britt, and Dietel. Accordingly, we also reverse the rejection of
independent claim 47 and dependent claims 48-53, standing therewith, over
Kravitz in view of Rajaram, Britt, Dietel, and Matsuda. Additionally, the
Examiner has not identified how Lee cures the noted deficiencies of Kravitz,
Rajaram, Britt, and Dietel. As such, we also reverse the rejection of claims
43 and 44 over Kravitz in view of Rajaram, Britt, Dietel, and Lee and the
rejection of claims 54 and 55 over Kravitz in view of Rajaram, Britt, Dietel,
Matsuda, and Lee.

V. CONCLUSION AND DECISION
The Examiner’s rejection of claims 36-44 and 46-55 under 35 U.S.C.
§ 103(a) is reversed.

REVERSED

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