Ex Parte Chen

Board of Patent Appeals and Interferences

Aug 21, 2012

11512000 (B.P.A.I. Aug. 21, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/512,000 08/29/2006 Qiang Chen 0180288 1033
25700 7590 08/21/2012
FARJAMI & FARJAMI LLP
26522 LA ALAMEDA AVENUE, SUITE 360
MISSION VIEJO, CA 92691
EXAMINER
CHI, SUBERR L
ART UNIT PAPER NUMBER
2829
MAIL DATE DELIVERY MODE
08/21/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte QIANG CHEN
____________

Appeal 2010-002376
Application 11/512,000
Technology Center 2800
____________

Before KARL D. EASTHOM, JONI Y. CHANG, and
ANDREW J. DILLON, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134 from the Examiner’s
decision to reject claims 1-7. (See Br. 2.) We have jurisdiction under 35
U.S.C. § 6(b).
We affirm.
Appeal 2010-002376
Application 11/512,000

2
STATEMENT OF THE CASE
The Specification describes an asymmetrical MOSFET (metal oxide
semiconductor field effect transistor) over a buried oxide layer which
provides isolation to the MOSFET. (See Spec. 5-6).
Claim 1 on appeal follows:
1. An asymmetric transistor comprising:
a semiconductor layer comprising a channel formed between a source
and a drain, said semiconductor layer being situated over a buried oxide
layer;
a drain-side channel portion having a higher carrier mobility and a
lower band gap than a source-side channel portion, thereby causing said
asymmetric transistor to have an increased drive current in an ON state and a
low leakage current in an OFF state.
Claims 1-7 stand rejected under 35 U.S.C. § 103(a) as obvious based
on Chen, U.S. 6,744,083 B2 (June 1, 2004) and An, U.S. 6,445,016 B1
(Sept. 3, 2002).
FACTUAL FINDINGS (“FF”)1
Chen discloses a MOSFET having an asymmetric channel comprising
a mesa structure on a conventional bulk silicon substrate 10. (See Chen,
Abstract, Fig. 1A.)
An discloses a buried oxide (BOX) layer between MOSFETs and an
underlying substrate. Such devices are known as silicon-on-insulator (SOI)
structures. (See, e.g., An, Abstract.) For example, An’s Figure 1 represents
an isolated SOI device 10, e.g., a MOSFET 10 on BOX layer 16 on silicon

1 The Decision relies upon additional factual findings not specifically
discussed in this section.
Appeal 2010-002376
Application 11/512,000

3
substrate 18. (An, col. 2, ll. 21-30.) An’s improved SOI structure reduces
floating body effects, and SOI structures include other circuit benefits, such
as electric isolation and reduction of parasitic capacitance – as compared to
bulk-type (i.e., non-SOI-type) MOSFETs or transistors. (See An, col. 1, ll.
8-31.)
ANALYSIS
There is no dispute that “Chen teaches all the limitations of claim 1
except for ‘a semiconductor layer over a buried oxide layer’” or that “An
teaches . . . a buried oxide layer.” (See Ans. 7 (quoting claim 1); accord Br.
7-8.)2 To combine Chen and An, the Examiner reasons as follows:
An teaches a motivation for using a buried oxide layer to yield
advantages in the areas of dielectric isolation, parasitic
capacitance, and overall circuit performance. The use of a
buried oxide layer yields these advantages over bulk materials
which do not use buried oxide layers. Chen teaches such a
conventional structure using only bulk materials, i.e., silicon.

(Ans. 8 (citing An at col. 1, ll. 16-21); accord FF.)
Appellant acknowledges that An and Chen disclose MOSFETs, and
that An discloses a MOSFET disposed over a BOX layer to obtain certain
benefits. (See Br. 6-8.) For example, Appellant states that “An is directed to
providing an SOI MOSFET having reduced floating body effects.” (Br. 8.)
However, Appellant argues that An’s MOSFET is symmetrical, while
Chen’s is not, and that An and Chen generally involve different structures
and solve different technical problems, so that skilled artisans would not

2 Based on Appellant’s arguments which rely on sole independent claim 1
(see Br. 9), claim 1 is selected as representative of claims 1-7.

Appeal 2010-002376
Application 11/512,000

4
have combined Chen with An. (See Br. 8-9.) These arguments fail to show
error.3
As the Examiner generally reasons, An’s SOI teachings, which
involve employing a BOX layer under a MOSFET and other transistors in
order to provide electrical isolation from the various devices on an
underlying substrate and other benefits as compared to bulk-type MOSFETs
such as Chen’s (see FF), render obvious the claimed combination. Appellant
does not direct attention to evidence showing that the recited or disclosed
BOX layer solves an unknown problem or represents an insurmountable
technical challenge. And as stated at the outset, the Specification reveals
that such a layer simply provides electrical isolation - as An similarly
teaches.4
Moreover, contrary to Appellant’s arguments regarding structural
differences, the relevant structures in An and Chen overlap in a simple
relationship. For example, An’s Figure 7a reveals a starting structure
showing an SOI wafer having an active layer 14 isolated by BOX layer 16
from underlying substrate 18. (An, col. 5, ll. 22-29.) Conceptually then,
Chen’s active layer 10 (silicon, col. 2, l. 36, Fig. 1A) would correspond to
An’s active layer 14 (silicon, col. 2, l. 24) (at least at the initial processing
steps).

3 The arguments do not allege that Chen or An is not analogous art. (But see
Ans. 7 (finding the art analogous).) In any event, the Specification reveals
that “[t]here is a continual effort to increase the performance of transistors,
such as MOSFETs.” (Spec. 1.) Chen and An constitute representative
examples of this “continual effort” to improve MOSFETs. (See FF.)

4 As originally filed, the claims did not recite a buried oxide layer. (See
Spec. 14-18 (original claims).)
Appeal 2010-002376
Application 11/512,000

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The record reflects that skilled artisans would have recognized that
modifying Chen’s bulk-type asymmetric MOSFET structure to create a
known SOI structure (which includes the recited BOX layer) would improve
electric isolation, reduce parasitic capacitance, reduce floating effects, and
generally enhance overall circuit performance, as An suggests and as the
Examiner reasons. (See FF; Ans. 7-8.)
Based on the foregoing discussion, Appellant’s arguments fail to show
error in the Examiner’s rejection of clams 1-7.
DECISION
The Examiner’s decision to reject claims 1-7 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

KMF