Ex Parte Chauvel et al

Board of Patent Appeals and Interferences

Jan 10, 2012

10830917 (B.P.A.I. Jan. 10, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte GERARD CHAUVEL, SERGE LASSERRE, DOMINIQUE
D’INVERNO, MAIJA KUUSELA, GILBERT CABILLIC, JEAN-
PHILLIPE LESOT, MICHEL BANATRE, JEAN-PAUL ROUTEAU,
SALAM MAJOUL, and FREDERIC PARAIN
____________________

Appeal 2010-001174
Application 10/830,917
Technology Center 2100
____________________

Before HOWARD B. BLANKENSHIP, THU A. DANG,
and ANDREW J. DILLON, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-001174
Application 10/830,917

2
I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-5 and 7-16 (App. Br. 5). Claims 6 and 17-21 have been cancelled
(id.). We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

A. INVENTION
Appellants’ invention relates to a system and method of dynamically
replacing a sequence of Java byte codes with a shorter more efficient micro-
sequence of complementary instruction set architecture (C-ISA) instructions
to make the system faster and more efficient; wherein, the micro-sequence
may include monitoring code that determines a performance characteristic
associated with the instruction being replaced (Abstract; Spec. ¶¶ [0018],
[0019] and [0035]).

B. ILLUSTRATIVE CLAIMS
Claims 1 and 8 are exemplary:
1. A method, comprising:

executing at least two instruction sets together in a
processor, a first set comprising Java-based instructions and a
second set comprising complementary instructions;

dynamically changing an instruction’s semantic based on
programmable information that is separate from the instruction,
wherein the dynamically changing includes replacing the Java-
based instructions by complementary instructions or by
standard Java-based instructions; the programmable
information indicates whether the instruction is to be directly
Appeal 2010-001174
Application 10/830,917

3
executed or whether an associated field contains a reference to a
micro-sequence;

implementing two program counters, a PC mode and a
micro-PC mode, wherein one of these two program counters is
active for fetching and decoding instructions;

setting a status register causes the micro-PC mode to be
active instead of the PC mode;

the dynamically changing the instruction occurs in the
PC mode and not in the micro-PC mode; and

implementing the method in a mobile communication
device.

8. A processor, comprising:

fetch logic that retrieves instructions from memory;

decode logic coupled to the fetch logic;

a vector table accessible to the decode logic and
containing a plurality of entries, each entry corresponding to an
instruction and having an associated configuration bit, the
configuration bit specifies whether the associated instruction is
to be replaced by an alternate sequence of instructions, and
those entries whose configuration bit specifies that the
associated instruction is to be replaced also include a pointer to
the alternate sequence of instructions;

wherein the vector table is dynamically programmable
for direct execution based on performance characteristics
associated with monitored instructions;

two modes of operation, a PC mode and a micro-PC
mode, wherein the associated instruction is replaced only in the
PC mode and not in the micro-PC mode regardless of the
configuration bit; and
Appeal 2010-001174
Application 10/830,917

4

the processor in contained in a mobile communication
device.

C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Heisch US 5,774,724 Jun. 30, 1998
Gee US 6,317,872 B1 Nov. 13, 2001
McCormick US 6,351,796 B1 Feb. 26, 2002
Sanchez US 6,477,666 B1 Nov. 05, 2002
Safford US 6,643,800 B1 Nov. 04, 2003
Dawson US 2004/0025145 A1 Feb. 05, 2004
Seal US 6,965,984 B2 Nov. 15, 2005
(filed Apr. 30, 2002)

Brown, What is Java? 1-3 (Jan. 3, 1999).

Claims 1, 4, 8, and 12-14 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Seal in view of Gee.
Claims 2, 3, 10, 15, and 16 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Seal in view of Gee and Safford.
Claims 5 and 9 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Seal in view of Gee, Safford, and Heish.
Claim 7 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Seal in view of Gee and Tremblay.
Claim 11 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Seal in view of Gee, Safford, and Tremblay.
Additionally, as to claims 1-5, 7-11, and 14-16, the Examiner
provisionally rejected claims 1 and 8 on the ground of non-statutory,
obviousness-type double patenting as being unpatentable over claims 1-24 of
Appeal 2010-001174
Application 10/830,917

5
copending Application 10/632,216 in view of Seal (Final Rej. 2-3; Ans. 4-
5); claims 2-4, 10, and 14-16 on the ground of non-statutory, obviousness-
type double patenting as being unpatentable over claims 1-24 of copending
Application 10/632,216 in view of Seal and Safford (Final Rej. 3; Ans. 5);
claims 5 and 9 on the ground of non-statutory, obviousness-type double
patenting as being unpatentable over claims 1-24 of copending Application
10/632,216 in view of Seal, Safford, and Heish (Final Rej. 3-4; Ans. 5-6);
and claims 7 and 11 on the ground of non-statutory, obviousness-type
double patenting as being unpatentable over claims 1-24 of copending
Application 10/632,216 in view of Seal and Tremblay (Final Rej. 4-5; Ans.
6). We note that the copending Application 10/632,216 went abandoned on
September 15, 2009; therefore, the provisional grounds of rejection are
moot.
Moreover, the Examiner has raised new grounds of rejections (Ans. 3
and 18-25); wherein, claims 8, 12, and 13 stand rejected under 35 U.S.C. §
103(a) as being unpatentable over Seal in view of Gee and McCormick;
claims 10, 15, and 16 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Seal in view of McCormick, Gee, and Safford; claim 9
stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Seal in
view of McCormick, Gee, Safford, and Heish; and claim 11 stands rejected
under 35 U.S.C. § 103(a) as being unpatentable over Seal in view of
McCormick, Gee, Safford, and Tremblay. Appellants present no arguments
against the corresponding new rejections of claims 9-11, 15, and 16 in the
Reply Brief, and as such, Appellants have waived any argument of error
regarding these rejections (see 37 C.F.R. 41.39 (b)(2)). Thus, we also
summarily sustain the rejections of claim 10, 15, and 16 under 35 U.S.C. §
Appeal 2010-001174
Application 10/830,917

6
103(a) over Seal in view of McCormick, Gee, and Safford; and claim 9
under 35 U.S.C. § 103(a) over Seal in view of McCormick, Gee, Safford,
and Heish; and claim 11 under 35 U.S.C. § 103(a) over Seal in view of
McCormick, Gee, Safford, and Tremblay.

II. ISSUES
The dispositive issues before us are whether the Examiner has erred in
determining that
1. the combination of Seal and Gee teaches or would have suggested
“executing at least two instructions sets together in a processor, a first set
comprising Java-based instructions and a second set comprising
complementary instructions” (claim 1, emphasis added);
2. the combination of Seal and Gee teaches or would have suggested
“a vector table accessible to the decode logic and containing a plurality of
entries, each entry corresponding to an instruction and having an associated
configuration bit, the configuration bit specifies whether the associated
instruction is to be replaced by an alternate sequence of instructions” (claim
8, emphasis added); and
3. the combination of Seal, Gee, and Safford teaches or would have
suggested “dynamically changing the instruction’s semantic comprises
including monitoring code within the instruction itself” (claim 2, emphasis
added).

Appeal 2010-001174
Application 10/830,917

7
III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Seal
1. Seal discloses a bytecode translation hardware 6 which receives
Java bytecodes to generate a sequence of corresponding ARM instructions
that are then passed to the processor core 4 (col. 6, ll. 10-17; Fig. 1).
2. A register 18 within the processor core 4 includes a flag 20
which controls whether the bytecode translation hardware 6 is currently
enabled or disabled (Fig. 1; col. 5, l. 60-col. 6, l. 1).
3. A register 19 within the processor core 4 includes a flag 21
which indicates whether the bytecode translation hardware is currently
active or inactive; wherein, when the flag 21 is active, it indicates that the
data processing system is currently executing Java bytecodes (col. 6, ll. 2-
20).
4. Certain Java bytecodes may require such extensive and abstract
processing that it would not be efficient to try and map these in hardware to
corresponding ARM instruction operations; therefore, when the byte code
translation hardware 6 encounters such a non-hardware supported bytecode,
a software instruction interpreter written in ARM native instructions
performs the processing (col. 6, ll. 32-40). Particularly, when a non-
hardware supported Java bytecode BC4 is encountered, it triggers an
exception with the bytecode translation hardware 6 that causes a look-up to
be performed using the bytecode value BC4 to act as an indexing pointer of
a table of pointers 24 which points to a code fragment 26 (Fig. 2, col. 6, ll.
60-67).
Appeal 2010-001174
Application 10/830,917

8
5. When the bytecode translation hardware 6 is present and
enabled by flag 20, then only those Java bytecodes that are non-hardware
supported will normally be referred out to the relevant code fragments
within the software instruction interpreter. Alternatively, when bytecode
translation hardware 6 is disabled by flag 20, then all of the Java bytecodes
will be referred to the software instruction interpreter (col. 6, ll. 43-51).
Safford
6. Safford discloses a microcode reprogrammer 70 is used to
reprogram any microinstruction or microinstruction sequence; wherein, the
reprogrammed microinstruction sequence constitutes a test that is to be run
on the computer microarchitecture (col. 3, ll. 28-34).

IV. ANALYSIS
Claims 1 and 4
Appellants provide arguments with respect to independent claim 1
(App. Br. 10-11). Accordingly, we select claim 1 as being representative of
the claims. See 37 C.F.R. § 41.37(c)(1)(vii).
Appellants contend that “Seal and Gee do not teach or fairly suggest
such a processor” that “‘execut[es] at least two instructions sets together in a
processor, a first set comprising Java-based instructions and a second set
comprising complementary instructions’” because “Seal appears to teach an
ARM processor 4 that executes only ARM instructions” and “Seal’s
bytecode translation hardware 6 only operates on Java bytecodes” (App. Br.
11).
However, the Examiner finds that, “when a Java bytecode is
translated, it is fed into the ARM decoder, where it is then executed on the
Appeal 2010-001174
Application 10/830,917

9
ARM processor” and, therefore, “one could argue that both instruction sets
are being executed by the same processor”; wherein, the “term ‘processor’ is
not necessarily defined to be as narrow as to be a processor core, and instead
encompasses a large variety of other hardware” (Ans. 26).
To determine whether the combination of Seal and Gee teaches or
would have suggested “executing at least two instructions sets together in a
processor, a first set comprising Java-based instructions and a second set
comprising complementary instructions” as recited in claim 1, we give the
claim its broadest reasonable interpretation consistent with the Specification.
See In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). However, we will
not read limitations from the Specification into the claims. In re Van Geuns,
988 F.2d 1181, 1184 (Fed. Cir. 1993).
Claim 1 does not place any limitation on what “processor” means,
includes, or represents. Thus, we give “processor” its broadest reasonable
interpretation as any system that processes instructions, as consistent with
the Specification and as specifically defined in claim 1.
Seal discloses a bytecode translation hardware which receives Java
bytecodes to generate a sequence of corresponding ARM instructions that
are then passed to the processor core (FF 1). We find that Seal’s system,
including the bytecode translation hardware coupled to the processor core, is
a processing system. As such, we agree with the Examiner’s position that
both sets of instructions, Java and ARM, are processed by the processing
system of Seal (Ans. 26).
In view of our claim construction above, we find that the combination
of Seal and Gee teaches providing “executing at least two instructions sets
together in a processor, a first set comprising Java-based instructions and a
Appeal 2010-001174
Application 10/830,917

10
second set comprising complementary instructions,” as specifically required
by claim 1.
Accordingly, we find that Appellants have not shown that the
Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a) over Seal in
view of Gee; and claim 4 depending from claim 1 which has been grouped
therewith.
Claims 8, 12, 13, and 14
Appellants provide arguments with respect to independent claim 8
(App. Br. 11-13). Appellants do not provide arguments with respect to
dependent claims 12, 13, and 14 (id.). Accordingly, we select claim 8 as
being representative of the claims. See 37 C.F.R. § 41.37(c)(1)(vii).
Appellants contend that “Seal and Gee do not teach or fairly suggest
such a processor” that includes “‘a vector table accessible to the decode
logic and containing a plurality of entries, each entry corresponding to an
instruction and having an associated configuration bit, the configuration bit
specifies whether the associated instruction is to be replaced by an
alternate sequence of instructions’”(App. Br. 12-13 (quoting claim 8))
because “Seal appears to teach a table of pointers accessible by the Java
translation hardware 6; however, the table of pointers does not include
information which indicates whether the Java bytecodes are to be replaced
by the ARM code fragments” (App. Br. 12). Appellants argue that “Seal
appears to teach that a flag in a register indicates whether the ARM
instructions are directly supplied to the processor or the bytecode translation
hardware maps the Java bytecodes to ARM instructions that are supplied to
the processor” (App. Br. 13). Appellants contend further that “Seal does
[not] teach a vector table containing a plurality of entries with each entry
Appeal 2010-001174
Application 10/830,917

11
having a configuration bit indicating whether the associated instruction is to
be replaced by an alternate sequence of instructions” (id.).
However, the Examiner finds that “[i]n Seal, the configuration bit
determines if the hardware translation logic is to be used or not, if so,
translation occurs and the instructions are executed” and “[i]f the hardware
translation logic is not to be used, then the vector table is accessed, and
micro-code instructions to replace the instruction are executed in its stead”
(Ans. 27-28). The Examiner notes “that the claim language[does not]
necessarily [require] the bit to be a part of the entry,” since “[t]he claim
[recites] that each entry has an associated bit” and “does not indicate that the
bit is unique to the entry, nor does it say that the bit is in the entry itself, the
fact that an association between an entry and a configuration bit can be made
is sufficient to read on the claim” (Ans. 28).
Claim 8 does not place any limitation on what “configuration bit”
means, includes, or represents, other than it is associated with an instruction
and specifies whether the associated instruction is to be replaced by an
alternate sequence of instructions. Thus, we give “configuration bit” its
broadest reasonable interpretation as any status bit that sets whether an
instruction is to be replaced by an alternate sequence of instructions, as
consistent with the Specification and as specifically defined in claim 8.
As noted supra, Seal discloses a data processing system 2 shown in
Figure 1, reproduced below including a bytecode translation hardware 6
which receives Java bytecodes to generate a sequence of corresponding
ARM instructions that are passed to the processor core 4 (FF 1). There are
two registers having two flags that are set; wherein, the first register (register
18) within the processor core includes a first flag (flag 20) which controls
App
App

whet
(FF 2
whic
activ
trans
the b
supp
elem
perfo
is us
supp
eal 2010-0
lication 10
her the by
) and the
h indicate
e or inacti
Seal’s F

Figure 1
lation hard

In opera
ytecode tr
orted byte
ent in Figu
rms the p
ed to point
orted Java

01174
/830,917
tecode tran
second reg
s whether
ve (FF 3).
igure 1 is r

depicts a
ware (col
tion, when
anslation h
code, a so
re 2, repr
rocessing (
to a code
bytecode
slation ha
ister (regi
the byteco

eproduced
data proce
. 4, ll. 21-2
the bytec
ardware e
ftware inst
oduced be
FF 4). In
fragment
BC4 (FF 4
12
rdware is
ster 19) in
de translat
below:
ssing syste
2).
ode transla
ncounters
ruction int
low written
particular
26 that wil
and 5).
currently e
cludes a se
ion hardw
m incorpo
tion hardw
such a non
erpreter sh
in ARM
, a look-up
l replace t
nabled or
cond flag
are is curr

rating byt
are 6 is e
-hardwar
own as a
native ins
table of p
he non-ha
disabled
(flag 21)
ently
ecode
nabled and
e
visual
tructions,
ointers 24
rdware

App
App

byte
hard
poin
supp
flag
instr
find
entri
flag
that
the b
eal 2010-0
lication 10
Seal’s F

Figure 2
codes (col

Therefor
ware, then
ters will be
orted with
is set to di
uction inte
the table o
es” of clai
Althoug
(flag 21) a
the first fla
ytecode tr
01174
/830,917
igure 2 is r

schematic
. 4, ll. 23-2
e, when th
the softw
used to r
relevant c
sable the b
rpreter wi
f pointers
m 8.
h Appellan
s the confi
g (flag 20
anslation h
eproduced
ally illustr
4).
e first flag
are instruc
eplace the
ode fragm
ytecode tr
ll translate
to be the “
ts base th
guration b
) found in
ardware (
13
below:
ates softw
is set to e
tion interp
Java bytec
ents (FF 5
anslation h
all of the
vector tab
eir argume
it, we agre
register 18
Ans. 27-2
are instruc
nable the
reter inclu
odes that
). Conver
ardware,
Java bytec
le … cont
nt upon de
e with the
which en
8) is the “a

tion interp
bytecode t
ding its ta
are non-ha
sely, when
then the so
odes (FF 5
aining a pl
signating
Examiner
ables and
ssociated
retation o
ranslation
ble of
rdware
the first
ftware
). We
urality of
the second
’s finding
disables
f

Appeal 2010-001174
Application 10/830,917

14
configuration bit” that “specifies whether the associated instruction is to be
replaced by an alternate sequence of instructions” as recited in claim 8. That
is, we find that “configuration bit” reads on Seal’s flag 20 (FF 2, 4, and 5).
We further agree with the Examiner’s finding that the claim does not
recite that “the bit to be a part of the entry,” since the claim “does not
indicate that the bit is unique to the entry, nor does it say that the bit is in the
entry itself”; therefore, “the fact that an association between an entry and a
configuration bit can be made is sufficient to read on the claim” (Ans. 28).
In view of our claim construction above, we find that the combination
of Seal and Gee teaches providing “a vector table accessible to the decode
logic and containing a plurality of entries, each entry corresponding to an
instruction and having an associated configuration bit, the configuration bit
specifies whether the associated instruction is to be replaced by an alternate
sequence of instructions,” as specifically required by claim 8.
Accordingly, we find that Appellants have not shown that the
Examiner erred in rejecting claim 8 under 35 U.S.C. § 103(a) over Seal in
view of Gee; and claims 12 -14 depending from claim 8 which have been
grouped therewith.
Because of our affirmance of the rejection of claims 8 and 12-14 as
being unpatentable over Seal in view of Gee, we also sustain the Examiner’s
cumulative rejection of claims 8, 12, and 13 based on unpatentability over
Seal in view of Gee and McCormick for the same reasons. We note that, in
light of this affirmance, the recitation of the additional reference
(McCormick) would not render a differing opinion.
Appeal 2010-001174
Application 10/830,917

15
Claim 2
Appellants contend that “Seal, Gee and Safford do not teach or fairly
suggest such a processor” that “‘dynamically chang[es] the instruction’s
semantic [which] comprises including monitoring code within the
instruction itself’” because “Safford appears to teach reprogramming
microcode to test the computer microarchitecture; however, Safford is silent
as changing the instruction’s semantics by including a monitoring code
within the instruction” (App. Br. 14 (quoting claim 2)).
However, the Examiner finds that “Safford teaches taking an
instruction, and modifying it with test code in order to test out the processor,
thus changing the instruction by inserting monitoring code” (Ans. 29).
Safford discloses a microcode reprogrammer is used to reprogram any
microinstruction/sequence; wherein, the reprogrammed microinstruction
sequence constitutes a test that is to be run on the computer
microarchitecture (FF 6). We find the microcode reprogrammer’s ability to
reprogram any microinstruction into a sequence that constitutes a test to be
run on the computer represents the inclusion of monitoring code within the
instruction itself (FF 6). That is, we find that “dynamically changing the
instruction’s semantic comprises including monitoring code within the
instruction itself” (claim 2) reads on the function of Safford’s microcode
reprogrammer.
Accordingly, we find that Appellants have not shown that the
Examiner erred in rejecting claim 2 under 35 U.S.C. § 103(a) over Seal in
view of Gee and Safford.
Appeal 2010-001174
Application 10/830,917

16
Claims 3, 5, and 7
Appellants argue that claims 3, 5, and 7 is patentable over the cited
prior art for the same reasons asserted with respect to claim 1 from which
they depend (App. Br. 14-15).
As noted supra, however, we find that the combination of Seal and
Gee at least suggests all the features of claim 1. We therefore affirm the
Examiner’s rejection of claims 3, 5, and 7 under 35 U.S.C. § 103 for the
same reasons expressed with respect to parent claim 1, supra.

Claims 9, 10, 11, 15, and 16
Appellants argue that claims 10, 15, and 16 are patentable over the
cited prior art for the same reasons asserted with respect to claim 8 from
which they depend (App. Br. 14-15).
As noted supra, however, we find that the combination of Seal and
Gee at least suggests all the features of claim 8. We therefore affirm the
Examiner’s rejection of claims 9, 10, 11, 15, and 16 under 35 U.S.C. § 103
for the same reasons expressed with respect to parent claim 8, supra.

V. CONCLUSION AND DECISION
We affirm the Examiner’s rejection of claims 1-5 and 7-16 under 35
U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

Appeal 2010-001174
Application 10/830,917

17
AFFIRMED

peb