Ex Parte Chauvel

Board of Patent Appeals and Interferences

Jan 26, 2012

11116522 (B.P.A.I. Jan. 26, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte GERARD CHAUVEL
___________

Appeal 2009-012981
Application 11/116,522
Technology Center 2100
____________

Before MAHSHID D. SAADAT, JEFFREY S. SMITH, and
ERIC B. CHEN, Administrative Patent Judges.

CHEN, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2009-012981
Application 11/116,522

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This is an appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1-20, all the claims pending in the application. We have jurisdiction
under 35 U.S.C. § 6(b). We reverse and enter a new ground of rejection
pursuant to our authority under 37 C.F.R. § 41.50(b).
STATEMENT OF THE CASE
Appellant’s invention relates to a processor which executes an
instruction that causes a comparison to be performed between contents of a
first register and contents of a second register and between the contents of
the first register and a predetermined value. (Abstract.) Such comparison
determines whether an attempted access to an array improperly targets a
location outside the array boundary. (Spec. ¶ [0006].)
Claim 1 is exemplary, with disputed limitations in italics:
1. A processor executing a plurality of instructions,
comprising:
an arithmetic logic unit (ALU); and
a plurality of registers coupled to the ALU;
wherein said processor executes an instruction that causes a
first comparison to be performed between contents of a first register
and contents of a second register and a second comparison to be
performed between the contents of the first register and a
predetermined value; and
wherein the instruction causes a first status bit to be set if either
of said comparisons results in a true condition and a second status bit
to be set if the first comparison determines that the contents of the
first register equal the contents of the second register.

Claims 1-17 and 19-20 stand rejected under 35 U.S.C. §102(b) as
being anticipated by Tremblay ‘383 (U.S. Patent No. 6,408,383).
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Claim 18 stands rejected under 35 U.S.C. §103(a) as being obvious
over Tremblay ‘383 and Tremblay ‘723 (U.S. Patent No. 6,014,723).
ANALYSIS
We are persuaded by Appellant’s arguments (App. Br. 12-13) that
Tremblay ‘383 does not disclose the disputed limitations “a first status bit to
be set if either of said comparisons results in a true condition” and “a second
status bit to be set if the first comparison determines that the contents of the
first register equal the contents of the second register,” as recited in
independent claim 1.
The Examiner found that the trap 510 of Tremblay ‘383 corresponds
to the claimed “first status bit” and that the trap 516 of Tremblay ‘383
corresponds to the claimed “second status bit.” (Ans. 5.) In particular, the
Examiner found that “[i]t is clear that any given processor would have an
ALU, comparison operations, and status register containing status bits,
whereas the status bits in status register would be set after comparison
operations.”1 (Ans. 12.) The Examiner also found that “[t]he ‘trap’, as an
internal interrupt routine must receive an interrupt request” that is
“considered as ‘status bit’.”2 (Ans. 12 (citation omitted).) We do not agree.
Tremblay ‘383 relates “to microprocessors, and more particularly, to a
boundary check acceleration instruction.” (Col. 1, ll. 7-9.) In one
embodiment, Figure 5 of Tremblay ‘383 illustrates a flow diagram of the

1 The Examiner cited Mano (M. MORRIS MANO, DIGITAL LOGIC AND
COMPUTER DESIGN 382-384 (Prentice Hall 1979)) as evidence.
2 The Examiner cited Vahid (FRANK VAHID & TONY GIVARGIS, EMBEDDED
SYSTEM DESIGN: A UNIFIED HARDWARE/SOFTWARE INTRODUCTION 148-153
(John Wiley & Sons, Inc. 2002)) as evidence.

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operation of a boundary check instruction 302. (Col. 7, l. 66 to col. 8, l. 1;
fig. 5.) From Figure 5, operation 508 determines whether R[rs1] is less than
zero and if so, a trap is performed at operation 510. (Col. 8, ll. 6-9; fig. 5.)
Also from Figure 5, operation 514 determines whether R[rs1] is greater than
R[rs2] and if true, a trap is performed at operation 516. (Col. 8, ll. 24-29;
fig. 5.) Although the Examiner cited to the trap performed at operation 510
and the trap performed at operation 516, the Examiner has not established
that the claim features of “a first status bit to be set if either of said
comparisons results in a true condition” and “a second status bit to be set if
the first comparison determines that the contents of the first register equal
the contents of the second register” are necessarily present in the boundary
check instruction 302 of Tremblay ‘383. See In re Robertson, 169 F.3d 743,
745 (Fed. Cir. 1999).
Thus, we do not agree with the Examiner that Tremblay ‘383
discloses the limitations “a first status bit to be set if either of said
comparisons results in a true condition” and “a second status bit to be set if
the first comparison determines that the contents of the first register equal
the contents of the second register,” as recited in independent claim 1.
Accordingly, we do not sustain the rejection of independent claim 1
under 35 U.S.C. §102(b). Claims 2-8 depend from independent claim 1.
Therefore, we do not sustain the rejection of these claims 2-8 under 35
U.S.C. § 102(b) for the same reasons discussed with respect to independent
claim 1.
Independent claims 9, 11 and 19 recite limitations similar to those
discussed with respect to independent claim 1. We do not sustain the
rejection of claims 9, 11 and 19, as well as claims 10, 12-17 and 20, which
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depend from claims 9, 11 and 19, for the same reasons discussed with
respect to claim 1.
Tremblay ‘723 was cited by the Examiner for teaching the additional
features of dependent claim 18. (Ans. 10-11.) However, the Examiner’s
application of Tremblay ‘723 does not cure the above-noted deficiencies of
Tremblay ‘383. Therefore, we do not sustain the rejection of claim 18 for
the same reasons discussed with respect to independent claim 11.

NEW GROUND OF REJECTION UNDER 37 C.F.R. § 41.50(b)
We enter the following new ground of rejection:
Claims 1, 9, 11 and 19 are rejected under 35 U.S.C. § 103(a) as being
obvious over Tremblay ‘383 and Mano.
Tremblay ‘383 teaches all the features of independent claim 1 except
“a first status bit to be set if either of said comparisons results in a true
condition” and “a second status bit to be set if the first comparison
determines that the contents of the first register equal the contents of the
second register.”
Mano teaches that “[i]t is sometimes convenient to supplement the
ALU with a status register where these status-bit conditions are stored for
further analysis.” (P. 382, § 9-7.) Furthermore, Mano teaches a 4-bit status
register (e.g., symbolized by C, S, Z and V) that are set or cleared as a result
of an operation performed in the ALU. (P. 382, § 9-7.) Bit C is set if the
output carry of the ALU is 1 and cleared if the output carry is 0 (i.e.,
corresponding to the claimed “a first status bit to be set if either of said
comparisons results in a true condition”). (P. 382, § 9-7.) Bit S is set if the
highest-order bit of the result in the output of the ALU is 1 and is cleared if
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the highest-order bit is 0 (i.e., the claimed “a second status bit to be set if the
first comparison determines that the contents of the first register equal the
contents of the second register”). (P. 382, § 9-7.)
Thus, the combination of Tremblay ‘383 and Mano is nothing more
than incorporating the known 4-bit status register of Mano (e.g., symbolized
by C, S, Z and V) with the known boundary check instruction 302 of
Tremblay ‘383, to yield predictable results. See KSR Int’l Co. v. Teleflex,
Inc., 550 U.S. 398, 416 (2007).
Therefore, independent claim 1 is obvious under 35 U.S.C. § 103(a)
over Tremblay ‘383 and Mano. Independent claims 9, 11 and 19 recite
limitations similar to those discussed with respect to independent claim 1.
Because the Board of Patent Appeals and Interferences is a review
body, rather than a place of initial examination, we have not reviewed
claims 2-8, 10, 12-18 and 20 to the extent necessary to determine whether
the combination of Tremblay ‘383, Mano and Tremblay ‘723 renders any of
these claims obvious. We leave it to the Examiner to determine the
appropriateness of any further rejections of dependent claims 2-8, 10, 12-18
and 20 under 35 U.S.C. § 103(a).
This decision contains new ground of rejection pursuant to 37 C.F.R.
§ 41.50(b).
37 C.F.R. § 41.50(b) provides that a “new ground of rejection
pursuant to this paragraph shall not be considered final for judicial review.”
37 C.F.R. § 41.50(b) also provides that Appellants, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new ground of rejection to
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avoid termination of proceedings (37 C.F.R. § 1.197 (b)) as to the rejected
claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the proceeding
will be remanded to the examiner ….
(2) Request rehearing. Request that the proceeding be
reheard under 37 C.F.R. § 41.52 by the Board upon the same
record ….

DECISION
The Examiner’s decision to reject claims 1-20 is reversed.
New ground of rejection has been entered under 37 C.F.R. § 41.50(b)
for claims 1, 9, 11 and 19, rejected as obvious over Tremblay ‘383 and
Mano.

REVERSED
37 C.F.R. § 41.50(b)

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