Ex Parte Chatterjee et al

Board of Patent Appeals and Interferences

Jun 16, 2009

10459681 (B.P.A.I. Jun. 16, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
__________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
__________

Ex parte BASAB CHATTERJEE, RICHARD L. GULDI,
and KEITH MELCHER
__________

Appeal 2009-000540
Application 10/459,681
Technology Center 2800
__________

Decided:1June 16, 2009
__________

Before ERIC GRIMES, RICHARD M. LEBOVITZ, and STEPHEN
WALSH, Administrative Patent Judges.

GRIMES, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134 involving claims to a method
and system for making semiconductor devices. The Examiner has rejected

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
Appeal 2009-000540
Application 10/459,681

the claims as obvious over the prior art. We have jurisdiction under 35
U.S.C. § 6(b). We reverse.
STATEMENT OF THE CASE
In making integrated circuit (IC) chips, “[t]ypically, a reticle having a
grid of several [IC chip] layouts is stepped or scanned across the entire
surface of the wafer while radiation is passed through the reticle to a resist
layer on the wafer” (Spec. 1, ¶ 2). The Specification discloses that this
process can result in partially completed device features near the edge of the
wafer, which can cause problems with other chips on the wafer during
subsequent processing (id. at 1-2, ¶¶ 3-4).
The formation of partially completed device features is illustrated in
the Specification’s Figure 2A, reproduced below:

The figure shows a reticle (205) positioned to expose patterns for
several IC chips on a resist layer (215) formed on a substrate (220) (id. at 11,
¶ 24). The figure shows that the pattern for the top-left chip is only partially
on the wafer, resulting in partially completed features.
The Specification discloses that the problem of partially completed
device features can be avoided by including “a window assembly located
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between a radiation source and the resist . . . [and] adjusting an exposure
width of the window assembly to prevent the radiation from exposing a
predefined blocking area of said resist” (id. at 5, ¶ 8). This process is
illustrated in the Specification’s Figure 2C, reproduced below:

The figure shows a window assembly (235) positioned between a
radiation source (240) and the reticle. The window assembly includes
shutters (255 and 260), one of which (255) has been positioned over the
opening (242) to reduce its width and prevent the radiation (230) from
exposing the part of the resist layer that would otherwise result in a partially
completed feature (id. at 13-14, ¶¶ 28-29).
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Application 10/459,681

Claims 1-4, 13-16, and 18-20 are on appeal.2 Claims 1 and 13 are
representative of the method and system claims and read as follows:
1. A method of manufacturing a semiconductor device,
comprising:
providing a resist layer over a substrate;
defining a blocking region on said substrate where said
overlying resist layer will not be exposed;
providing a reticle having device patterns formed therein
wherein said device patterns define an exposure zone;
providing a radiation source and a window assembly wherein
said window assembly is located between said radiation source and said
resist;
positioning said reticle between said radiation source and said
resist wherein said exposure zone of said reticle is at least partially over said
blocking region; and
adjusting an exposure width of said window assembly to
prevent radiation from said radiation source from exposing said blocking
region wherein adjusting includes moving one or more shutters of said
window assembly as a function of said window assembly’s location above
said substrate.

13. A system for manufacturing a semiconductor device,
comprising:
a reticle having device patterns formed therein that define an
exposure zone, said reticle positionable over a resist layer formed over a
substrate;
a radiation source;
a window assembly located between said radiation source and
said resist layer, said window assembly configured to be adjusted to an
exposure width to prevent radiation from said radiation source from
exposing portions of said resist layer within said exposure zone and
overlying a predefined blocking area of said substrate; and

2 Claim 8 is also pending but does not stand rejected by the Examiner
(Office action mailed Feb. 23, 2005, page 1).
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said window assembly includes one or more controllers
configured to move said one or more shutters to a predefined position as a
function of said predefined location.
OBVIOUSNESS
Issue
The Examiner has rejected claims 1-4, 13-16, and 18-20 under 35
U.S.C. § 103(a) as obvious in view of Nei3 and Tsuo4 (Ans. 4). The
Examiner finds that Nei teaches all of the limitations of the claimed system
and method, including a “blocking means . . . used to prevent irradiation on
desired areas of the resist layer” (Ans. 5), but “does not explicitly teach that
the blocking means is on the substrate” (id.).
The Examiner finds that Tsuo “teaches masked areas (44) that will act
as blocking means and these areas are not exposed to the ion beam (38)”
(id.). The Examiner concludes that it would have been obvious “to use a
blocking means on the substrate because this will allow one to exploit the
chemical and physical differences in the respective regions of the substrate”
(id.).
Appellants contend that neither Nei nor Tsuo teaches the limitation of
“adjusting an exposure width of said window assembly . . . [by] moving one
or more shutters of said window assembly as a function of said window
assembly’s location above said substrate,” as recited in claim 1, or the
comparable limitation in claim 13, the other independent claim on appeal
(App. Br. 11-12).5

3 Nei et al., U.S. Patent 6,342,941 B1, issued Jan. 29, 2002.
4 Tsuo, U.S. Patent 5,041,361, issued Aug. 20, 1991.
5 Citations are to Appellants’ “Second Amended Brief,” filed Feb. 26, 2008.
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Application 10/459,681

The issue with respect to this rejection is: Did the Examiner err in
concluding that Nei’s process includes a step of preventing radiation from
exposing a blocking region by moving the shutter(s) of a window assembly,
as a function of the window assembly’s location above a substrate, to adjust
an exposure width of the window assembly?
Findings of Fact
1. Claim 1 includes the steps of “defining a blocking region on said
substrate where said overlying resist layer will not be exposed” and
“adjusting an exposure width of said window assembly to prevent radiation
from said radiation source from exposing said blocking region wherein
adjusting includes moving one or more shutters of said window assembly as
a function of said window assembly’s location above said substrate” (claim
1).
2. The Specification states that “[b]locking areas are defined as those
areas of the resist where it is undesirable to transfer device patterns onto. . . .
Because it is more likely that partially completed features would be formed
in the perimeter region of the wafer, blocking areas are often located around
the edges of the substrate.” (Spec. 8-9, ¶ 18.)
3. Nei discloses a “a lithography process and apparatus used for the
fabrication of items such as ICs” (Nei, col. 1, ll. 19-20).
4. Nei’s Figure 1 is reproduced below:
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The figure shows “a simplified schematic diagram showing the
exposure apparatus” of one embodiment of Nei’s system (id. at col. 4, ll. 42-
43).
5. Nei’s system includes “an exposure light source 14, which emits
irradiation light IL” (id. at col. 4, ll. 53-54).
6. Nei’s irradiation light is directed, via a series of mirrors and lenses
(30, 32, 34, 36, and 38) onto reticle R (id. at col. 5, ll. 37-49).
7. The irradiation light exposes a “photosensitive material coated as
resist on the wafer W” according to the pattern of the reticle (id. at col. 5, ll.
26-27).
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8. Nei discloses that “[p]rovided between the light source 14 and the
mirror 30 is a control section in the form of a shutter 40, which opens and
closes the irradiation light IL light path for selected time periods” (id. at col.
5, ll. 50-53).
9. Nei discloses that “the wafer stage 12, with wafer W loaded on it,
is moved in two dimensions . . . , in sequence. Repeated exposures are
performed, to effect multiple exposures of the reticle R pattern image, in
sequence, on one wafer, in the so-called step-and-repeat exposure
technique.” (Id. at col. 7, ll. 34-39.)
10. Nei discloses that in the step-and-repeat exposure technique, “the
shutter 40 is repeatedly opened to pass irradiation light IL, and closed to
block it, in synchronization with the movements of the wafer stage 12” (id.
at col. 7, ll. 39-42).
11. The Examiner concludes that Tsuo would have made obvious
modifying Nei by “us[ing] a blocking means on the substrate” (Ans. 5).
12. A “blocking means on the substrate” is not a limitation of either
of the independent claims on appeal.
13. Tsuo discloses a method of making IC chips by depositing a thin
film of amorphous silicon on a substrate and “exposing portions of the
amorphous silicon to low-energy oxygen ion beams to oxidize the
amorphous silicon at . . . selected portions. The nonoxidized portions are
then removed by etching.” (Tsuo, abstract.)
14. Tsuo discloses that one method of making a pattern of oxidized
and unoxidized regions on “the amorphous silicon resist material . . . is to
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expose selected parts of the resist material 24 to oxygen ion beams 34
through a mask 36, as illustrated in FIG. 3” (id. at col. 8, ll. 50-55).
15. Tsuo discloses that the “masked areas 44 of the resist surface 26,
of course, are not exposed to the ion beams 38, so the . . . resist materials in
those areas 44 under the blocked areas 38 of mask 36 remain unoxidized and
unchanged. Therefore, the oxidized regions . . . are virtually impervious to
hydrogen plasma etching.” (Id. at col. 9, ll. 16-23.)
Principles of Law
“[D]uring examination proceedings, claims are given their broadest
reasonable interpretation consistent with the specification.” In re Hyatt, 211
F.3d 1367, 1372 (Fed. Cir. 2000).
[T]he PTO applies to the verbiage of the proposed claims the
broadest reasonable meaning of the words in their ordinary
usage as they would be understood by one of ordinary skill in
the art, taking into account whatever enlightenment by way of
definitions or otherwise that may be afforded by the written
description contained in the applicant’s specification.
In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997).
“The test of obviousness vel non is statutory. It requires that one
compare the claim’s ‘subject matter as a whole’ with the prior art ‘to which
said subject matter pertains.’” In re Ochiai, 71 F.3d 1565, 1569 (Fed. Cir.
1995) (quoting 35 U.S.C. § 103).
A proper § 103 analysis requires “a searching comparison of the
claimed invention – including all its limitations – with the teaching of the
prior art.” Ochiai, 71 F.3d at 1572.
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“In rejecting claims under 35 U.S.C. § 103, the examiner bears the
initial burden of presenting a prima facie case of obviousness.” In re
Rijckaert, 9 F.3d 1531, 1532 (Fed. Cir. 1993).
Analysis
The Examiner finds that “[b]ecause the shutter (40) is controlled to
pass and block light, which will adjust the exposure width of the window
assembly, based on the movement of the substrate in relation to the window
assembly, [Nei] teaches the claimed moving of one or more shutters as a
function of the window assembly’s location above the substrate” (Ans. 5).
We do not agree that Nei’s shutter meets the relevant limitations of
claims 1 and 13. Claim 1 requires “defining a blocking region on said
substrate where said overlying resist layer will not be exposed” and
“adjusting an exposure width of said window assembly to prevent radiation
. . . from exposing said blocking region” by moving shutters as a function of
the window assembly’s location above the substrate.
Similarly, claim 13, which defines a system, requires a “window
assembly configured to be adjusted to an exposure width to prevent radiation
. . . from exposing portions of said resist layer . . . overlying a predefined
blocking area of said substrate” via controllers configured to move shutters
to different locations as a function of the window assembly’s location.
The Specification defines “blocking areas” to mean “those areas of the
resist where it is undesirable to transfer device patterns onto.” (Claim 1
recites a “blocking region” rather than a “blocking area” but the two terms
are reasonably interpreted to mean the same thing.)
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Thus, the claims require that the shutters on the window assembly are
moved, based on the window assembly’s location with respect to the
substrate, to prevent exposure of a part of the substrate that would otherwise
be exposed to the reticle’s pattern by adjusting the exposure width of the
window assembly.
Nei’s shutter opens and closes during the step-and-repeat exposure
technique. That is, Nei’s shutter is closed while the wafer stage moves the
wafer, opens to allow the illumination light to expose part of the wafer to the
reticle pattern image, closes again while the wafer is moved to a new
position, and so on. While Nei’s shutter arguably adjusts an exposure width,
in the sense that it changes the exposure width from zero to fully open and
back again, that adjustment does not prevent exposure of a “blocking area”
or “blocking region,” as recited in claims 1 and 13; i.e., a part of the
substrate that would otherwise be exposed to the reticle’s pattern.
The Examiner has pointed to no disclosure in Nei or Tsuo that would
suggest the desirability of preventing part of the wafer substrate from being
exposed to the reticle pattern image during IC manufacture. Therefore, the
Examiner has not shown that the method of claim 1 or the system of claim
13, which require preventing exposure of a “blocking area” or “blocking
region,” would have been prima facie obvious based on the cited references.
CONCLUSION OF LAW
The Examiner erred in concluding that Nei’s process includes a step
of preventing radiation from exposing a blocking region by moving the
shutter(s) of a window assembly, as a function of the window assembly’s
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location above a substrate, to adjust an exposure width of the window
assembly.
SUMMARY
We reverse the rejection of claims 1-4, 13-16, and 18-20 under 35
U.S.C. § 103(a) as obvious in view of Nei and Tsuo.

REVERSED

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