Ex Parte Chatterjee et al

Patent Trial and Appeal Board

Nov 13, 2013

11041935 (P.T.A.B. Nov. 13, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/041,935 01/26/2005 Siddhartha Chatterjee YOR920040441US1 6395
48150 7590 11/13/2013
MCGINN INTELLECTUAL PROPERTY LAW GROUP, PLLC
8321 OLD COURTHOUSE ROAD
SUITE 200
VIENNA, VA 22182-3817
EXAMINER
DOAN, DUC T
ART UNIT PAPER NUMBER
2185
MAIL DATE DELIVERY MODE
11/13/2013 PAPERPAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte SIDDHARTHA CHATTERJEE, JOHN A. GUNNELS, and
LEONARDO R. BACHEGA
____________

Appeal 2013-006063
Application 11/041,935
Technology Center 2100
____________

Before ALLEN R. MacDONALD, JOHN A. JEFFERY, and
CAROLYN D. THOMAS, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
This application returns to us after another panel of this Board1
affirmed the Examiner’s decision to reject then-pending claims 1-23. Ex
parte Chatterjee, No. 2009-008854 (BPAI Mar. 3, 2011) (“Bd. Dec’n”),
reh’g denied (BPAI July 11, 2011) (expanded panel). Prosecution reopened
after that decision, and Appellants now appeal under 35 U.S.C. § 134(a)

1 The panel for the earlier appeal was Judge Jeffery, Judge Thomas, and
Judge Lucas (no longer available)—a panel that was expanded on rehearing
to include Judge MacDonald and Judge Moore.
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from the Examiner’s subsequent rejection of claims 1, 3, 6-12, 14, 16-21,
and 24-30. We have jurisdiction under 35 U.S.C. § 6(b). We reverse.

STATEMENT OF THE CASE
Appellants’ invention increases computational efficiency by retrieving
data such that stalling does not occur due to exceeding an allowable number
of cache misses. See generally Spec. 2-4. Claim 1 is illustrative:
1. A method of increasing computational efficiency in a computer
comprising:
a plurality of cores, each said core comprising:
at least one central processing unit (CPU) with at least one associated
functional processing unit (FPU), said FPU comprising a plurality of
working registers as loaded and unloaded by a load store unit (LSU) with a
minimal latency;
a first memory device servicing said at least one FPU, said first
memory device having a memory line larger than an increment of data
consumed by said at least one FPU, said first memory device having a pre-
set number of allowable outstanding data misses between the core and a next
higher level before a processing in said FPU stalls; and between the core and
a next higher level before a processing in said FPU stalls; and at least one
other memory device servicing said at least one FPU via said first memory
device, said method comprising:
in a processing occurring in said FPU, providing instructions in a
kernel controlling said FPU so that data not currently needed for processing
can be retrieved in predetermined manner in a line of retrieved data; and
in a data retrieval, as controlled by said kernel and as responding to an
allowable outstanding data miss for said processing, including a provision
that at least one word of data in a line of retrieved data retrieved from said at
least one other memory device comprises at least one data word additional to
data of an allowable outstanding data miss, said additional data comprising
data that will at least one of prevent said pre-set number of outstanding data
misses from being exceeded, reduce a chance that said pre-set number of
outstanding data misses will be exceeded, and delay a time at which said
pre-set number of outstanding data misses is exceeded.

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THE REJECTIONS2
The Examiner rejected claims 1, 3, 6-12, 14, 16-21, and 24-30 under
35 U.S.C. § 112, second paragraph as indefinite. Ans. 5-6.3
The Examiner rejected claims 1, 3, 6-12, 14, 16, 18, 20, 21, and 24-30
under 35 U.S.C. § 103(a) as unpatentable over Maher (US 2005/0251644
A1; published Nov. 10, 2005; filed May 6, 2004), Chaudhry (US
2002/0188807 A1; published Dec. 12, 2002), and Yang (US 5,379,393;
issued Jan. 3, 1995). Ans. 7-19.
The Examiner rejected claims 17, 19, and 29 under 35 U.S.C. § 103(a)
as unpatentable over Maher, Chaudhry, Yang, and Johnson (US
2004/0139340 A1; published July 15, 2004). Ans. 19-21.

THE INDEFINITENESS REJECTION
The Examiner finds that because the recited “fetching and processing
data and additional data by instructions / code of a vector / matrix program”
is said to contradict Appellants’ arguments regarding the unimportance of
the actual matrix data retrieved in connection with the invention, the

2 Because the Examiner’s objections to the Specification and drawings in the
Answer (Ans. 4-5, 22) are petitionable—not appealable—matters, they are
not before us. See MPEP § 706.01 (“[T]he Board will not hear or decide
issues pertaining to objections and formal matters which are not properly
before the Board.”); see also MPEP § 1201 (“The Board will not ordinarily
hear a question that should be decided by the Director on petition . . . .”).
3 Throughout this opinion, we refer to (1) the Final Rejection mailed
February 22, 2012; (2) the Appeal Brief filed August 20, 2012
(supplemented September 25, 2012) (“App. Br.”); (3) the Examiner’s
Answer mailed February 15, 2013 (“Ans.”); and (4) the Reply Brief filed
March 31, 2013 (“Reply Br.”).
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Examiner cannot ascertain the “scope and intention” of the independent
claims which renders them indefinite. Fin. Rej. 4, 21; Ans. 6, 22-25.
Appellants argue that skilled artisans would understand from the
Specification that the claimed invention optimizes efficiency by
orchestrating retrieving data from L3 to L1 cache such that stalls are
prevented “in the shadow” of cache misses. App. Br. 14-25; Reply Br. 1-6.
To this end, Appellants explain, each line retrieved from L3 cache not only
has data responsive to an allowed miss, but also additional data for a miss
that has not yet occurred—a line that is said to be consumed in two stages as
shown in Appellants’ Figure 2. App. Br. 17-25. According to Appellants,
this intermixing pre-fetched and fetched data for current allowable misses on
the same L1 cache line prevents stalling by operating “in the shadow” of
cache misses, but the specific details of how the kernel moves data from the
L1 cache to specific working registers is insignificant in this regard. App.
Br. 14-25; Reply Br. 1-6.

ISSUE
Has the Examiner erred in rejecting claim 1 by finding that the recited
data retrieval and processing steps render the claim indefinite under § 112,
second paragraph?

ANALYSIS
We will not sustain the Examiner’s indefiniteness rejection of
independent claim 1 for the reasons indicated by Appellants. App. Br. 14-
25; Reply Br. 1-6. Despite the Examiner’s perception that the recited data
retrieval and processing steps run counter to Appellants’ arguments
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regarding the type of data retrieved (Fin. Rej. 4, 21; Ans. 6, 22-25), we agree
with Appellants that skilled artisans would understand from the
Specification that intermixing pre-fetched and fetched data for current
allowable misses on the same L1 cache line would at least reduce the chance
of exceeding a pre-set number of outstanding misses as claimed. The
specific type of data (e.g., “vector” or “matrix”), or how it is moved from L1
cache to specific working registers, is irrelevant to the fundamental feature
of the claimed invention, namely including additional data in a line of data
retrieved responsive to an allowed miss to perform at least one of the three
associated functions that increase computational efficiency as claimed. The
Examiner’s contention that pre-fetching cache-line data is well known in the
art (Ans. 23-24) is unavailing, for this finding not only undermines the
Examiner’s contention that skilled artisans would not understand the recited
additional data retrieval to render the claim indefinite, but the Examiner does
not squarely address the particular manner in which this data is retrieved and
processed to increase computational efficiency as claimed. In short, because
skilled artisans would reasonably understand what is claimed when
considered in light of the Specification, the claims are definite.
Therefore, we are persuaded that the Examiner erred in rejecting (1)
independent claim 1; (2) independent claims 11, 16, and 24 which recite
commensurate limitations; and (3) the dependent claims for similar reasons.4

4 We note in passing, however, that the “functional processing unit (FPU)”
recited in claim 1 differs from the term in the Specification that uses that
acronym, namely the floating-point units and their associated register files.
See Spec. 19:22-23 (defining “FPU” to mean both floating-point units and
their register files). The Examiner should consider whether this
inconsistency renders the claim indefinite under § 112, second paragraph
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THE OBVIOUSNESS REJECTION OVER MAHER, CHAUDHRY, AND
YANG

The Examiner finds that Maher’s CPU has at least one associated FPU
with registers that are loaded and unloaded as claimed in claim 1, but lacks
the recited (1) pre-set number of allowable outstanding data misses, and (2)
kernel instructions, but cites Chaudhry and Yang for respectively teaching
these features in concluding that the claim would have been obvious. Ans.
7-8, 25-28. According to the Examiner, not only would fetching and storing
vector data in Maher’s primary memory have been obvious because cache
misses and fetching cache lines is known in the art, but it would have also
been obvious to pipeline various operations in Maher, including queuing
outstanding misses, in view of Chaudhry. Ans. 26-27. The Examiner also
equates Yang’s fetching data blocks to fetching cache lines—a teaching that
is said to “complement” the teachings of Maher and Chaudhry. Ans. 28.
Appellants argue that not only does cited prior art not retrieve a data
line responsive to an allowed miss that incorporates additional data directed
to a future miss as claimed, but Maher actually teaches away from its
proposed modification by using a processor-based approach in lieu of cache
memory. App. Br. 26-38; Reply Br. 6-9.

should prosecution follow this opinion. The Examiner should also consider
whether the coined term “in a shadow of misses” renders claims 6, 14, and
27 indefinite regarding the precise scope of this somewhat unusual term used
in the context of those claims. See App. Br. 25 (equating “‘in the shadow of
misses’” to “at the very edge of stalling out”).
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ISSUE
Under § 103, has the Examiner erred by finding that Maher,
Chaudhry, and Yang collectively would have taught or suggested (1) in FPU
processing, providing instructions in a kernel controlling the FPU so that
data not currently needed for processing can be retrieved in a predetermined
manner in a line of retrieved data, and (2) in a data retrieval, responding to
an allowable outstanding data miss for processing occurring in an FPU,
where at least one word of data in a line of data retrieved from at least one
other memory device comprises at least one data word in addition to data of
an allowable outstanding data miss, where the additional data will at least
one of (i) prevent exceeding a preset number of outstanding data misses; (ii)
reduce a chance of exceeding that number; and (iii) delay a time at which the
number is exceeded as recited in claim 1?

ANALYSIS
Claims 1 and 21
We begin by noting several key distinctions between the prior art
rejection of claim 1 in the earlier appeal and this appeal. First, claim 1 was
narrowed in various key respects after the earlier Board decision, including
the last two clauses as follows (strikethroughs and underlining to show
deletions and insertions):

1. A method of increasing computational efficiency in a computer
comprising . . . .
in a processing occurring in said FPU, providing instructions in a
kernel controlling said FPU so that data not currently needed for processing
can be retrieved in a predetermined manner in a line of retrieved data; and
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in a data retrieval, as controlled by said kernel and as responding to an
allowable data miss for said processing, including a provision that at least
one additional word of data in a line of retrieved data retrieved from said at
least one other memory device comprises at least one data word additional to
data of an allowable outstanding data miss, said additional data comprising
data that will at least one of prevent said pre-set number of outstanding data
misses from being reached exceeded, reduce a chance that said pre-set
number of outstanding data misses will be reached exceeded, and delay a
time at which said pre-set number of outstanding data misses is reached
exceeded.

Prelim. Amd’t filed Sept. 7, 2011.
Second, the prior art rejections in the earlier appeal involved different
prior art and statutory grounds, namely, an anticipation rejection over
Southwell which is not cited in a rejection in this appeal, and various
obviousness rejections citing Southwell in combination with other
references, only one of which (Johnson) is cited in a rejection in this appeal
and not at issue here. Compare Bd. Dec’n, at 3 (summarizing rejections in
earlier appeal) with App. Br. 2 (summarizing rejections in this appeal).
Therefore, the earlier panel’s findings regarding Southwell’s anticipating
then-pending claim 1 are irrelevant to this appeal that involves different
claim limitations, different rejections, and different prior art. Accordingly,
the Examiner’s reference to Southwell and the earlier panel’s affirming the
rejections based on that reference in connection with the obviousness
rejection in the present appeal (Ans. 245-25) has little bearing on the distinct
issues that are before us in this appeal.6

5 Although the Examiner’s discussion of the Board’s findings regarding
Southwell on page 24 of the Answer pertains to the § 112 rejection, the
Examiner nonetheless refers to this discussion in connection with the
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Turning to the merits of the Examiner’s obviousness rejection, we
agree with Appellants that the cited prior art does not teach or suggest the
processing and data retrieval steps recited in the last two clauses of claim 1
noted above. First, the Examiner concedes that Maher and Chaudhry lack
these disputed steps, but nonetheless takes the position that because Yang
fetches blocks that include additional data for subsequent processes, it would
have been obvious “to include [a] data retrieving cache memory system such
that the system cooperates with numerical programs in an efficient[]
manner” in the Maher/Chaudhry system. Ans. 8. In reaching this
conclusion, the Examiner’s rejection cites Yang’s Background section that
discusses known uses of cache memories, and in particular the effect of
blocking data on cache performance. Id. (citing Yang, col. 1, l. 10–col. 2, l.
34). In the Answer’s Response to Arguments, however, the Examiner cites
different passages from Yang regarding the effect of fetching data in
blocks—blocks that are said to correspond to cache lines—on speeding
cache performance. Ans. 28 (citing Yang, col. 20, l. 52–col. 21, l. 10; col.
22, ll. 30-68).
To be sure, the Examiner’s cited passages from Yang discuss blocking
application programs to improve cache memory vector processing and
examining the increased speed resulting from adding cache memories into
an MM-model vector computer, as well as the effects of cache line size on

obviousness rejection. See, e.g., Ans. 25 (referring to the discussion of
“item A above”).
6 Accord App. Br. 33 (“The Examiner’s reliance . . . on Southwell is also
misplaced, since the Examiner does not include this reference in the
rejection of record, presumably because the revised claim [1] incorporates
details that precluded the Examiner from carrying this reference over from
the previous prosecution.”) (underlining omitted).
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performance. See Yang, col. 1, l. 10–col. 2, l. 34; col. 20, l. 52–col. 21, l.
10; col. 22, ll. 30-68. Nevertheless, we fail to see how these passages teach
or suggest the particular recited processing and data retrieval steps that
include providing the recited additional data word in a line of data retrieved
responsive to an outstanding data miss, where the additional data will
perform at least one of the three recited functions regarding exceeding a
preset number of outstanding data misses.
That is, even if the cited references were combinable as proposed, and
even if we were to accept the Examiner’s position that Maher fetches data
from secondary memory to store in primary memory (Ans. 25-26 (citing
Maher ¶¶ 0013, 0027-29, 0078-80)), and that fetching cache lines responsive
to cache misses is known in the art, we still fail to see how the cited prior art
teach or suggests the particular data processing and retrieval steps recited in
claim 1.
Therefore, we are persuaded that the Examiner erred in rejecting (1)
independent claim 1; (2) independent claims 11, 16, and 24 which recite
commensurate limitations; and (3) dependent claims 3, 6-10, 12, 14, 18, 20,
21, 25-28, and 30 for similar reasons. Since this issue is dispositive
regarding our reversing the rejection of these claims, we need not address
Appellants’ other arguments.

THE OTHER OBVIOUSNESS REJECTION
Since the Examiner has not shown that Johnson cures the deficiencies
noted above regarding the independent claims, we will not sustain the
obviousness rejection of dependent claims 17, 19, and 29 (Ans. 19-21) for
similar reasons.
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CONCLUSION
The Examiner erred in rejecting claims 1, 3, 6-12, 14, 16-21, and
24-30 under §§ 112 and 103.

ORDER
The Examiner’s decision rejecting claims 1, 3, 6-12, 14, 16-21, and
24-30 is reversed.

REVERSED

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