Ex Parte Chang et al

Board of Patent Appeals and Interferences

Sep 5, 2012

11629769 (B.P.A.I. Sep. 5, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte YEOW K. CHANG and WENG FEI MOO
____________

Appeal 2010-004601
Application 11/629,769
Technology Center 2100
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Before JOHN A. JEFFERY, STANLEY M. WEINBERG, and
GLENN J. PERRY, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-004601
Application 11/629,769

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Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-7. We have jurisdiction under 35 U.S.C. § 6(b). We
affirm-in-part.

STATEMENT OF THE CASE
Appellants’ host controller transfers data over a Universal Serial Bus
(USB) system in frames and micro-frames. Data is transferred only during
micro-frames corresponding to a packet transfer descriptor’s active bit
values. See generally Abstract. Claim 1 is illustrative:
1. A host controller, for use in transferring data over a bus
communication system in frames and micro-frames, in which each data
transfer is described by a packet transfer descriptor, wherein a packet
transfer descriptor for a data transfer includes at least a number of data
packets indicative of a size of said data and a bit map, such that said data is
transferred according to the packet transfer descriptor only during those
micro-frames of a frame which correspond to bits of the bit map for which
the bit value has been set to an active value.

THE REJECTION
The Examiner rejected claims 1-7 under 35 U.S.C. § 103(a) as
unpatentable over Terada (US 6,757,770 B1; June 29, 2004) and INTEL
CORP., ENHANCED HOST CONTROLLER INTERFACE SPECIFICATION FOR
UNIVERSAL SERIAL BUS, Rev. 1.0 (Mar. 2002) (“Intel”). Ans. 3-7.1

1 Throughout this opinion, we refer to (1) the Appeal Brief filed July 20,
2009; (2) the Examiner’s Answer mailed October 30, 2009; and (3) the
Reply Brief filed December 30, 2009.
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CONTENTIONS
The Examiner finds that Terada’s host controller transfers data over a
bus communication system and has every recited feature of representative
claim 1 except for a packet transfer descriptor including a number of data
packets indicative of data size and a bit map, but cites Intel’s split
transaction isochronous transfer descriptor (siTD) as teaching (1) data size
via the siTD’s “Total Bytes to Transfer” and/or “T-count” fields shown in
Intel’s Figure 3-5, and (2) a bit map via the “μFrame C-mask” and/or
“μFrame S-mask” fields. Ans. 3-4, 8. Intel’s siTD functionality is also said
to transfer data according to the packet transfer descriptor only during
micro-frames corresponding to the map’s active bit values when “C-Mask”
or “S-Mask” bits are set to “1” in micro-frames 4, 6, and 7 in Intel’s Table 4-
17. Ans. 4, 8-9. Based on these collective teachings, the Examiner
concludes that claim 1 would have been obvious. Ans. 3-4, 8-9.
Appellants argue that Intel’s isochronous transfer descriptor (iTD)
does not include a size and bit map as claimed since the iTD does not
include the software scheduling table information for siTDs in Intel’s Table
4-17. App. Br. 6-7. Appellants add that this table’s bit map merely allows
the host controller to change the state of execution from “Do Start Split” to
“Do Complete Split,” but does not limit transferring data only during
corresponding micro-frames as clamed. App. Br. 8-9. Appellants also argue
various other recited limitations summarized below. App. Br. 10-11; Reply
Br. 8-10.

Appeal 2010-004601
Application 11/629,769

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ISSUES
Under § 103, has the Examiner erred by finding that Terada and Intel
collectively would have taught or suggested:
(1)(a) a packet transfer descriptor including at least a number of data
packets indicative of data size and a bit map, and (b) transferring data
according to the packet transfer descriptor only during micro-frames
corresponding to the map’s active bit values as recited in claim 1?
(2) a packet transfer descriptor for data transfer to interrupt endpoints
specifies a variable polling rate as recited in claim 3?
(3) the host controller operates as a slave on the memory bus as
recited in claim 4?

ANALYSIS
Claims 1, 2, 5, and 6
On this record, we find no error in the Examiner’s obviousness
rejection of representative claim 1. As noted above, the Examiner relies
principally on Intel’s siTD for teaching (1) data size via the siTD’s “Total
Bytes to Transfer” and/or “T-count” fields shown in Intel’s Figure 3-5, and
(2) a bit map via the “μFrame C-mask” and/or “μFrame S-mask” fields.
Ans. 4, 8. Appellants, however, argue that Intel’s iTD does not teach the
recited data size and bit map. App. Br. 6-7. We emphasize “iTD” here, for
Appellants’ arguments do not squarely address the Examiner’s position
regarding Intel’s siTD apart from merely alleging that the iTD lacks the
siTD’s software scheduling information in Table 4-17. App. Br. 8. Even
assuming, without deciding, that this is the case, we are nonetheless
unpersuaded by this argument since it does not squarely address—let alone
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persuasively rebut—the Examiner’s findings regarding Intel’s siTD noted
above.
Nor are we persuaded of error in the Examiner’s position that Intel’s
siTD functionality transfers data according to the packet transfer descriptor
only during micro-frames corresponding to the map’s active bit values when
“C-Mask” or “S-Mask” bits are set to “1” in micro-frames 4, 6, and 7 in
Intel’s Table 4-17. Ans. 4, 8-9 (citing Intel 113 (Table 4-17)). Although the
Examiner acknowledges that these bits change the state of execution from
running “start splits” to “complete splits” as Appellants contend (App. Br.
8), the Examiner nonetheless finds that these state changes involve
corresponding data transfers as evidenced by the Compaq USB
specification2 (Ans. 8-9)—a finding that is likewise unrebutted. We
therefore see no reason why Intel does not at least suggest transferring data
according to the siTD only during micro-frames 4, 6, and 7 in Table 4-17
associated with their respective “start split” and “complete split” transactions
as the Examiner indicates. See Ans. 8-9. Although Intel’s bit map ignores
the “1” “C-Mask” bits in micro-frames “0” and “1” in Table 4-17 (and
therefore does not execute a “complete split” in those micro-frames) as the
Examiner acknowledges (Ans. 9 (citing Intel 113, ¶ 2, ll. 2-3)), we
nonetheless see no error in the Examiner’s position at least to the extent that
it is based solely on the data transfers in micro-frames 4, 6, and 7.3

2 The Examiner refers to page 200 of this reference which is cited on page 3
of the Answer.
3 Although the Examiner contends that the recited “comprising” language
does not limit the host controller’s transferring data during other operation
modes (Ans. 9), claim 1 does not contain the term “comprising.” Rather,
independent claim 5 contains that term. Nevertheless, this is a distinction
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Appellants’ arguments that data is “possibly” transferred during any micro-
frame (and therefore not transferred only during the micro-frames designated
in the packet transfer descriptor) (App. Br. 9) are not only speculative and
unsubstantiated,4 but are not commensurate with the scope of the claim
which does not preclude the limited data transfers according to Intel’s siTD
in micro-frames 4, 6, and 7 noted above.
Lastly, although Appellants contend that Intel teaches away from
using the disclosed specification with Terada’s host controller (Reply Br. 6-
7), this combinability argument was raised for the first time in the Reply
Brief. Compare Reply Br. 4-7 with App. Br. 5-7. This new argument is
therefore waived as untimely. See Ex parte Borden, 93 USPQ2d 1473, 1474
(BPAI 2010) (informative) (“[T]he reply brief [is not] an opportunity to
make arguments that could have been made in the principal brief on appeal
to rebut the Examiner’s rejections, but were not.”).
We are therefore not persuaded that the Examiner erred in rejecting
representative claim 1, and claims 2, 5, and 6 not separately argued with
particularity.

without a meaningful difference here, for we are unpersuaded of error in the
Examiner’s position at least to the extent that it is based solely on the data
transfers in micro-frames 4, 6, and 7 as noted above.
4 Appellants’ permissive word choice is telling in this regard. See, e.g., App.
Br. 9 (“[T]here does not appear to be any restriction on when the data of a
packet transfer descriptor may be transferred, even if some of it might be
transferred during a specific micro-frame indicated by the software
scheduling information of Table 4-17.” (emphases added)); see also id.
(“[T]he data transferred possibly may be transferred during any micro-frame,
so that the data transfer operation does not appear to be limited to only a
micro-frame(s) designated in a packet transfer descriptor.” (emphases
added)).
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Claims 3 and 7
We also sustain the Examiner’s rejection of representative claim 3
reciting the packet transfer descriptor for data transfer to interrupt endpoints
specifies a variable polling rate. The Examiner finds that the particular “S-
Mask” values in Intel’s Table 4-11, namely the hexadecimal values “01h”
and “02h,” cause queue head polling to occur every first or second micro-
frame, respectively. Ans. 4, 9-10 (citing Intel 88, § 4.10.7, Table 4-11).
Accord Intel Table 4-11 (noting that queue head S-Mask values “01h” and
“02h” indicate that endpoint transactions should be executed during micro-
frames “0” and “1,” respectively).
Based on this functionality, the Examiner reasons that an S-Mask
value of “FFh” would cause polling every frame due its binary equivalent
value “11111111,” and an S-Mask value of “11h” and its binary equivalent
value “01010101” likewise causes polling every other frame. Ans. 10.
These variations are said to teach a variable polling rate as claimed. Id.
We see no error in this reasoning, for apart from merely alleging that
Intel’s polling functionality in Section 4.10.7 does not teach a variable
polling rate (App. Br. 10-11; Reply Br. 8), Appellants do not squarely
address—let alone persuasively rebut—the Examiner’s position noted
above.5
We are therefore not persuaded that the Examiner erred in rejecting
representative claim 3, and claim 7 not separately argued with particularity.

5 Although Appellants cite Intel page 115, § 4.15, ¶ 3, in connection with the
arguments for claim 3 (App. Br. 10), this citation is inapposite to the
Examiner’s position since the Examiner did not rely on this passage in
connection with this claim. See Ans. 5, 9-10.
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Claim 4
We will not, however, sustain the Examiner’s rejection of claim 4
reciting, in pertinent part, that the host controller operates as a slave on the
memory bus. The Examiner’s contention that the term “slave” is “non-
functional descriptive labeling” and therefore has no patentable weight (Ans.
5, 10) is untenable. The term “slave” has a recognized meaning in the art,
namely that which is controlled by something else.6 Accord Spec. 1:22-29,
4:17-29 (noting that by acting as bus system slaves, host devices and
controllers need not master the bus). Therefore, when interpreted in light of
this plain meaning and in light of the Specification, we agree with
Appellants that the Examiner’s refusing to give the term “slave” patentable
weight in claim 4 is erroneous. App. Br. 11; Reply Br. 9-10.
We are therefore persuaded that the Examiner erred in rejecting claim
4.

CONCLUSION
Under § 103, the Examiner did not err in rejecting claims 1-3 and 5-7,
but erred in rejecting claim 4.

ORDER
The Examiner’s decision rejecting claims 1-7 is affirmed-in-part.

6 STEVEN M. KAPLAN, WILEY ELECTRICAL & ELECTRONICS DICTIONARY 716
(2004); see also MCGRAW-HILL DICTIONARY OF ELECTRICAL & COMPUTER
ENGINEERING 530 (2004) (defining “slave” as “[a] terminal or computer that
is controlled by another computer” or “a device whose motions are governed
by instructions from another machine”).
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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