Ex Parte Chan et al

Patent Trial and Appeal Board

Nov 12, 2014

12135079 (P.T.A.B. Nov. 12, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte SHANY-I CHAN, YU-KUO CHIANG, SHIH-DA WU,
PATRICK BEAULIEU, WILLIAM S. HERZ, LI-LING CHOU,
and CHING-YEE FENG
____________________

Appeal 2012-008590
Application 12/135,079
Technology Center 2100
____________________

Before JOHN A. EVANS, WILLIAM M. FINK, and
ELIZABETH A. LaVIER, Administrative Patent Judges.

FINK, Administrative Patent Judge.

DECISION ON APPEAL
Appellants1 seek our review under 35 U.S.C. § 134(a) of the
Examiner’s final rejection of claims 1–6, 9–19, and 21–23. We have
jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 According to Appellants, the real party in interest is the NVIDIA
Corporation. (App. Br. 3.)
Appeal 2012-008590
Application 12/135,079

2

STATEMENT OF THE CASE
Appellants’ Invention
Appellants’ invention relates to a computer graphics system detecting
the connection of a television set. (Spec. ¶ 1; Abstract.)2 Specifically,
Appellants claim systems and methods for hot-plugging a video connector to
a computer system based on the voltage state of a ground pin. (Spec. ¶ 5.)

Claims on Appeal
Claims 1 and 12 are the independent claims on appeal. Claim 1 is
illustrative of Appellants’ invention and is reproduced below with disputed
limitations emphasized:
1. A computer device comprising:
a video connector;

a processing unit; and

a hot-plugging detection circuit coupled between the
processing unit and a ground pin of the video connector,
wherein the hot-plugging detection circuit includes a transistor
switch electrically connected to the ground pin and a detection
node that is at a first voltage level when the transistor switch is
in a first state and at a second voltage level when the transistor
switch is in a second state,

wherein the processing unit determines a hot-plugging of
the video connector based on the voltage level at the detection
node.

2 Our decision refers to Appellants’ Appeal Brief filed January 23, 2012
(“App. Br.”); the Examiner’s Answer mailed March 14, 2012 (“Ans.”);
Appellants’ Reply Brief filed May 11, 2012 (“Reply Br.”); Final Office
Action mailed June 10, 2011 (“Final Act.”); and the original Specification
filed June 6, 2008 (“Spec.”).
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Application 12/135,079

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Evidence Considered
Murata US 6,232,678 B1 May 15, 2001
Lee US 7,053,864 B1 May 30, 2006
Mathur US 7,190,191 B1 Mar. 13, 2007
Ichimura US 2007/0121020 A1 May 31, 2007

Examiner’s Rejection
Claims 1–6, 9–19, 21–23 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Ichimura, Lee, Murata, and Mathur. (Ans. 4–17.)

Issue on Appeal
Based on Appellants’ arguments, the issue on appeal is whether the
combination of Ichimura, Lee, Murata, and Mathur teaches “a hot-plugging
detection circuit coupled between the processing unit and a ground pin of the
video connector, where the hot-plugging detection circuit includes a
transistor switch electrically connected to the ground pin and a detection
node that is at a first voltage level when the transistor switch is in a first
state and at a second voltage level when the transistor switch is in a second
state,” as recited by claim 1. (See App. Br. 10–12, 14.)

ANALYSIS
With respect to Appellants’ independent claims 1 and 12, the
Examiner relies on the combination of Ichimura, Lee, Murata, and Mathur.
(Ans. 5–8.)
Appellants dispute the Examiner’s factual findings. (App. Br. 10–12.)
Specifically, Appellants argue that “none of Ichimura, Lee, Murata, or
Mathur teaches or suggests the limitations of a hot-plugging detection circuit
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Application 12/135,079

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coupled between the processing unit and a ground pin of the video
connector.” (Id. at 10.) Appellants argue that, because the cited references
alone or in combination do not teach or suggest every limitation of claim 1,
the combination cannot render claim 1 obvious. (Id. at 12.)
On the record before us, we must agree with Appellants. In
responding to Appellants’ arguments with respect to the disputed limitation,
the Examiner finds Ichimura teaches a host/computer capable of detecting
the plugging in of an “S-video connector” (Ans. 20 (citing Ichimura, Fig.
4)), and finds that the S-video connector contains a “ground pin” (Ans. 5,
22).
However, as Appellants point out, the disputed limitation does not just
require a ground pin, but also
includes a transistor switch electrically connected to the
ground pin and a detection node that is at a first voltage level
when the transistor switch is in a first state and at a second
voltage level when the transistor switch is in a second state.

(Reply Br. 7 (quoting Claim 1) (emphasis added).) We note that claim 12
contains a similar limitation. (See App. Br. 15 (Claim 12).) Thus, at
minimum, the claims require the ground pin to be connected to a transistor
switch. This enables the computer device to detect hot-plugging a video
connector. (See Spec. ¶¶ 18–19 & Fig. 2A.)
We find no evidence cited by the Examiner that teaches or suggests a
ground pin connected to a transistor switch as required by claim 1. While
the Examiner does find transistor switches are disclosed in Mathur (Ans. 6),
we find no cited evidence that teaches or suggests this switch be connected
the ground pin in Ichimura’s S-video connector. In fact, there is no
discussion by the Examiner at all as to the role of the ground pin(s) in the S-
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video connector, much less a reasoned basis articulated why its connection
to a transistor switch, would be obvious in view of the cited evidence. See
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007) (citing In re Kahn,
441 F.3d 977, 988 (Fed. Cir. 2006)).
On this record, Appellants have persuaded us the Examiner erred in
rejecting claim 1. Accordingly, we do not sustain the Examiner’s rejection
of independent claim 1. Independent claim 12 includes similar limitations
directed to the hot-plugging detection circuit and ground pin; therefore, for
the same reasons, we do not sustain the rejection of independent claim 12.
With respect to dependent claims 2–6, 9–11, 13–19, and 21–23 we reverse
the rejections of these claims as well.

DECISION
We reverse the Examiner’s final rejection of claims 1–6, 9–19, and
21–23.

REVERSED

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