Ex Parte CHAEDownload PDFPatent Trial and Appeal BoardMay 3, 201612979199 (P.T.A.B. May. 3, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 12/979, 199 12/27/2010 127226 7590 05/05/2016 Birch, Stewart, Kolasch & Birch, LLP P.O. Box 747 Falls Church, VA 22040-0747 FIRST NAMED INVENTOR Ji-Eun CHAE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 6655-021OPUS1 2602 EXAMINER LAM, TUAN THIEU ART UNIT PAPER NUMBER 2842 NOTIFICATION DATE DELIVERY MODE 05/05/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): mailroom@bskb.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JI-EUN CHAE 1 Appeal2014-006907 Application 12/979,199 Technology Center 2800 Before DEBRA K. STEPHENS, JASON V. MORGAN, and MICHAEL J. ENGLE, Administrative Patent Judges. ENGLE, Administrative Patent Judge. DECISION ON APPEAL Appellant appeals under 35 U.S.C. § 134(a) from a rejection of claims 1, 2, and 5-7. Claims 3 and 4 were previously cancelled, and claim 8 is objected to as being dependent upon a rejected claim. We have jurisdiction over the rejected claims under 35 U.S.C. § 6(b ). We AFFIRM. Technology According to Appellant, a typical liquid crystal display includes an output buffer unit. App. Br. 3; Spec. i-fi-12-9. The invention relates to whether electrodes within that output buffer unit overlap. E.g., Claim 1. 1 According to Appellant, the real party in interest is LG Display Co., Ltd. App. Br. 1. 1 Appeal2014-006907 Application 12/979,199 Representative Claim Claim 1 is representative and reproduced below with the key limitation emphasized: 1. A shift register comprising: a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, wherein at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof being smaller than a second area at which the gate electrode overlaps with a second electrode thereof, wherein a clock pulse is applied to the first electrode, wherein the at least one of the plurality of switching device includes: a plurality of sub-first electrodes formed parallel to one another, a connecting first electrode connecting the plurality of sub-first electrodes, a plurality of sub-second electrodes formed parallel to one another, and a connecting second electrode connecting the plurality of sub-second electrodes, and wherein the plurality of sub-first electrodes are formed to overlap with the gate electrode, the connecting first electrode is formed not to overlap with the gate electrode, and the plurality of sub-second electrodes and the connecting second electrode are formed to overlap with the gate electrode. Rejection Claims 1, 2, and 5-7 stand rejected under 35 U.S.C § 103(a) as being unpatentable over Pak et al. (US 2006/0001637 Al; Jan. 5, 2006) in view of Wei et al. (CN 101552294 A; Oct. 7, 2009). Final Act. 2. 2 Appeal2014-006907 Application 12/979,199 ISSUE Did the Examiner err in concluding that "the connecting second electrode [is] formed to overlap with the gate electrode," as recited in claim 1, is obvious over Pak in view of Wei? ANALYSIS Claims 1, 2, and 5-7 Appellant argues the Examiner erred in rejecting claim 1 as obvious because neither Pak nor Wei teaches or suggests "the connecting second electrode [is] formed to overlap with the gate electrode." App. Br. 4. For example, Appellant contends that Figure 2 of Wei depicts a connecting second electrode not overlapping the gate electrode. Id. (citing Wei 5, Fig. 2). We agree with Appellant that given the limited record before us, including no certified translation of Wei, the Examiner has not shown that either Pak or Wei explicitly discloses a connecting second electrode overlapping the gate electrode. See, e.g., Wei Fig. 2A, p.5 (a mechanical translation of which is attached as an Appendix to this opinion). However, the Examiner does not rely on the express disclosures of Pak or Wei for this limitation. Rather, the Examiner determines that a person of ordinary skill in the art "would have ... recognized that by controlling the overlapping area with the gate electrode, the power consumption can be adjusted." Final Act. 3, 5. The Examiner cites Pak paragraphs 72, 84, 120, and 131 for support that a person of ordinary skill would have known that changing the level of overlap would change the power consumption. Final Act. 5. Based on this, the Examiner determines that the level of overlap between the second connecting electrode and the 3 Appeal2014-006907 Application 12/979,199 gate electrode employed by an artisan of ordinary skill would have been dependent upon the power consumption needs of the particular application at hand. Id. at 3, 5. "Therefore, outside of any non-obvious results, the obvious[ ness] of controlling overlapping between the ... second connecting electrode with the gate electrode will not be patentable under [35 U.S.C. §] 103(a)." Id. Appellant calls the Examiner's determination "a generic statement," yet in the Appeal Brief does not otherwise substantively address the Examiner's conclusion on this point, such as by disputing whether a person of ordinary skill would know power consumption could be adjusted by changing the level of overlap or by identifying "non-obvious results" as suggested by the Examiner. App. Br. 4. In the Reply Brief, Appellant newly argues that Wei changes the ratio of overlap in other ways, such as by changing the number of sub-first or sub- second electrodes (which Appellant calls "fingers"). Reply Br. 3. For example, Appellant contends that Figure 2A of Wei shows nine fingers on electrodes 204 yet ten finger for electrodes 206. Id. Yet pursuant to 37 C.F.R. § 41.41(b)(2), "[a]ny argument raised in the reply brief which was not raised in the appeal brief, or is not responsive to an argument raised in the examiner's answer, ... will not be considered by the Board for purposes of the present appeal, unless good cause is shown." Here, the Examiner raised the same theory in both the Final Rejection and the Answer, and cited support from the same paragraphs of Pak. Final Act. 3, 5; Ans. 4--5, 6. Thus, we are not persuaded by Appellant's argument that the Examiner's answer raised a new issue in the Answer. Reply Br. 2. Moreover, Appellant's Reply Brief fails to persuasively address the Examiner's 4 Appeal2014-006907 Application 12/979,199 underlying determination that a person of ordinary skill would have known that power consumption could be adjusted by changing the level of overlap and that there would be only obvious results from creating overlap with the second connecting electrode. Accordingly, we sustain the Examiner's rejection of claim 1, and claims 2 and 5-7, which contain the disputed recitation. See App. Br. 5; 37 C.F.R. § 41.37(c)(l)(iv) (2012). DECISION For the reasons above, we affirm the Examiner's decision rejecting claims 1, 2, and 5-7. 5 Appeal2014-006907 Application 12/979,199 AFFIRMED APPENDIX The following is a mechanical translation, obtained using Google patent translation tool, of an excerpt from Wei starting at the end of page 4 and ending at the beginning of page 6 (http://google.com/patents/ CN101552294A?cl=en; retrieved Apr. 18, 2016): DISCLOSURE [I]s provided a bottom gate thin film transistor, which can improve the cooling capacity of the component. The present invention provides an active array substrate, it can be solved by the reliability of self-heating caused by the problem of poor. The present invention proposes a bottom-gate thin film transistor including a gate electrode, a gate insulating layer, a semiconductor layer, a plurality of source and a plurality of drain. A gate insulating layer disposed on the gate. The semiconductor layer disposed on the gate insulating layer, and Located above the gate. The ratio of the semiconductor layer and the gate area of approximately from 0.001 to 0.9. A source electrode electrically connected to each other, and the drain is electrically connected to each other, and the source and drain are electrically insulated from each other. Bottom-gate thin film transistor according to the present embodiment of the invention, said gate electrode, for example, a rectangular gate electrode, and the semiconductor layer, for example, a rectangular semiconductor layer. In accordance with a bottom-gate thin film transistor according to an embodiment of the present invention, the gate of the rectangle is a square, for example, the gate electrode, and the semiconductor layer is a semiconductor layer, for example, a square. In accordance with a bottom-gate thin film transistor according to an embodiment of the present invention, for example, a rectangular gate of the rectangular gate electrode, and the semiconductor layer is a semiconductor layer such as a rectangle. 6 Appeal2014-006907 Application 12/979,199 Bottom-gate thin film transistor in accordance with an embodiment of the present invention, the extending direction of the source and drain e.g. parallel to two short sides of rectangular gate, the gate and the source and drain, respectively, from two rectangular long side extended to the semiconductor layer. In accordance with a bottom-gate thin film transistor according to an embodiment of the present invention, the above-described example, the source and drain are alternately arranged on the semiconductor layer. In accordance with a bottom-gate thin film transistor according to an embodiment of the present invention, the rectangular gate and said at least one side of the rectangular semiconductor layer side, for example, the shortest distance greater than 3 microns. Bottom-gate thin film transistor in accordance with an embodiment of the present invention, the extending direction of the source and drain e.g. parallel to each other, and the source and drain, respectively, from the two opposite sides of the rectangular gate extending onto the semiconductor layer. In accordance with a bottom-gate thin film transistor according to an embodiment of the present invention, the above-described example, the source and drain are alternately arranged on the semiconductor layer. Bottom-gate thin film transistor according to the present embodiment of the invention, said semiconductor layer, for example, an amorphous silicon layer. Bottom-gate thin film transistor in accordance with an embodiment of the present invention, said semiconductor layer, for example, a plurality of semiconductor pattern independent of each other, and to maintain a gap between any two adjacent semiconductor pattern. In accordance with a bottom-gate thin film transistor according to an embodiment of the present invention, the above-described example of the gap is about 3 microns to 100 microns. 7 Copy with citationCopy as parenthetical citation