Ex Parte Carpenter et al

Patent Trial and Appeal Board

Apr 25, 2017

13041721 (P.T.A.B. Apr. 25, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/041,721 03/07/2011 BRIAN ASHLEY CARPENTER TI-69590 5620
23494 7590 04/27/2017
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS, TX 75265
EXAMINER
NADAV, ORI
ART UNIT PAPER NUMBER
2811
NOTIFICATION DATE DELIVERY MODE
04/27/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BRIAN ASHLEY CARPENTER,
CHRISTOPHER J. SANZO, and
WILLIAM TODD HARRISON
Appeal 2016-004109
Application 13/041,7211
Technology Center 2800
Before BEVERLY A. FRANKLIN, MICHAEL P. COLAIANNI, and
BRIAN D. RANGE, Administrative Patent Judges.
RANGE, Administrative Patent Judge.
DECISION ON APPEAL
SUMMARY
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1, 2, 6, and 11. We have jurisdiction. 35 U.S.C.
§ 6(b). We AFFIRM.
1 According to the Appellants, the real party in interest is Texas Instruments
Incorporated. Appeal Br. 3.
Appeal 2016-004109
Application 13/041,721
STATEMENT OF THE CASE2
Appellants describe the invention as relating to semiconductor power
converter packages comprising stacked die assemblies. Spec. 11.
Appellants’ design provides multi-die packaging for Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs or also referred to as
FETS) and seeks to minimize the area of the power converter packaging
while also providing improved performance. Id. at 2-4. Claim 1,
reproduced below with emphasis added to certain key recitations, is
illustrative of the claimed subject matter:
1. A stacked die power converter package, comprising:
a lead frame including a die pad and a plurality of package
pins;
a first die including a low side LS power transistor
attached to said die pad as part of a stack;
a first metal clip attached to one side of said first die, said
first metal clip coupled to at least one of said plurality of package
pins;
a second die including a high side HS power transistor
attached to another side on said first metal clip as part of the
stack;
a second metal clip is attached to one side of said second
die; and
a controller die is aligned with and attached to said
second metal clip, wherein said controller die is monolithic
integrated, mounted as a top die of the stack and is coupled to
both a first control node of said LS power transistor and a second
control node of said HS power transistor.
2 In this decision, we refer to the Final Office Action mailed March 13, 2015
(“Final Act.”), the Appeal Brief filed August 11, 2015 (“Appeal Br.”), and
the Examiner’s Answer mailed October 22, 2015 (“Ans.”).
2
Appeal 2016-004109
Application 13/041,721
Appeal Br. 22 (Claims App’x).
REFERENCES
The Examiner relies upon the prior art below in rejecting the claims
on appeal:
Hinrichsmeyer et al.
(hereinafter “Hinrichsmeyer”)
Saito et al.
(hereinafter “Saito”)
Otremba et al.
(hereinafter “Otremba”)
Ewe et al.
(hereinafter “Ewe”)
US 4,996,587
US 7,271,477 B2
US 7,732,929 B2
US 7,821,128 B2
Feb. 26, 1991
Sept. 18,2007
June 8, 2010
Oct. 26, 2010
REJECTIONS
The Examiner maintains the following rejections on appeal:
Rejection 1. Claims 1, 2, 6, and 11 under 35 U.S.C. § 112 as failing
to comply with the written description requirement. Ans. 2—3.
Rejection 2. Claims 1, 2, 6, and 11 under 35 U.S.C. § 103 as
unpatentable over Hinrichsmeyer or Saito each in view of Ewe and Otremba.
Id. at 3.
Rejection 3. Claims 1, 2, 6, and 11 under 35 U.S.C. § 103 as
unpatentable over Otremba in view of Hinrichsmeyer, Saito, and Ewe. Id.
at 6.
The Examiner has withdrawn the prior rejection of claims 1, 2, 6, and
11 under 35 U.S.C. § 112 based upon there being no support in Figure 3 for
“said controller die is monolithic integrated, mounted as a top die of the
stack” as recited in claim 1. Ans. 2. The Examiner maintains the written
description rejection discussed below.
3
Appeal 2016-004109
Application 13/041,721
Appellants also indicate that they are seeking appeal of a rejection
based on indefiniteness under 35 U.S.C. § 112. Appeal Br. 8, 17. Our
understanding of the Final Office Action and the Answer is that the
Examiner is not making a rejection based on indefiniteness. Ans. 11. We
therefore do not address indefmiteness.
ANALYSIS
Rejection 1. The Examiner rejects claims 1, 2, 6, and 11 under 35
U.S.C. § 112 as failing to comply with the written description requirement
based upon there being no support in Figure 3 for “a controller die arranged
in a straight line (i.e. aligned) with said second metal clip, as recited in claim
1.” Ans. 3. Appellants argue that this recitation is supported by, for
example, Figure 3 of the Specification. Appeal Br. 16. Figure 3 is
reproduced below.
Figure 3 is a cross sectional depiction of the power converter package
further in the Specification. Spec. 13.
4
Appeal 2016-004109
Application 13/041,721
The Examiner maintains that controller die 130 is not aligned with the
second metal clip 126 because alignment requires that “at least one edge of
controller die 130 must be arranged along the same vertical line as one of the
edges of the second metal clip 126.” Ans. 9. The Examiner’s construction
of “aligned with and attached to said second metal clip” is unduly narrow.
The Specification discusses alignment of the controller die and second clip
(Spec. 136), and this discussion does not support such a narrow
construction. Rather, alignment in the context of the Specification merely
appears to require that surfaces of the controller die and clip be near each
other and positioned so that the clip can attach. Figure 3 shows such an
embodiment. We therefore do not sustain this rejection.
Rejections 2 and 3. The Examiner rejects claims 1, 2, 6, and 11 as
obvious over Hinrichsmeyer or Saito each in view of Ewe and Otremba
(rejection 2) and also rejects these same claims as obvious over Otremba in
view of Hinrichsmeyer, Saito, and Ewe (rejection 3). Ans. 3, 6.
We review the appealed rejections for error based upon the issues
identified by the Appellants and in light of the arguments and evidence
produced thereon. Cf. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential) (cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed.
Cir. 2011) (“it has long been the Board’s practice to require an applicant to
identify the alleged error in the examiner’s rejections”)). After considering
the evidence presented in this Appeal and each of Appellants’ contentions,
we are not persuaded that Appellants identify reversible error. Thus, we
affirm the Examiner’s obviousness rejections for the reasons expressed in
5
Appeal 2016-004109
Application 13/041,721
the Final Office Action and the Answer. We add the following primarily for
emphasis.
Appellants argue rejections 2 and 3 together, and argue all claims as a
group. See Appeal Br. 18. Therefore, consistent with the provisions of 37
C.F.R. § 41.37(c)(l)(iv) (2013), we limit our discussion to claim 1, and all
other claims on appeal stand or fall together with claim 1.
To support rejection 2, the Examiner finds that Hinrichsmeyer and
Saito each teach a stacked die power converter package including most
recitations of claim 1. Ans. 3—5 (providing citations to Hinrichsmeyer and
Saito). The Examiner finds that Hinrichsmeyer and Saito do not teach that
the first die is a low side LS power transistor, the second die is a high side
HS power transistor, and the third die is the controller die. Id. at 4—5. The
Examiner finds, however, that Ewe teaches top die 12 can be used as a
power die or controller die. Id. at 5 (providing citations to Ewe). The
Examiner also finds that Otremba teaches using a first die 16 as a low side
LS power transistor and a second die 17 as a high side HS power transistor.
Id. (providing citations to Otremba). The Examiner thus concludes:
It would have been obvious to one of ordinary skill in the art at the
time the invention was made to use the first die as a low side LS
power transistor, the second die as a high side HS power transistor
and the third die as the controller die, in the devices of Hinrichsmeyer
et al. and Saito et al. in order to improve the devices’ characteristics
and to reduce the size of the device when using the devices in power
applications. The combination is motivated by the teaching of
Otremba et al. who point out the advantages of using the first die as a
low side LS power transistor and the second die as a high side HS
power transistor.
Id. A preponderance of the evidence supports the Examiner’s findings and
conclusion.
6
Appeal 2016-004109
Application 13/041,721
To support rejection 3, the Examiner finds that Otremba teaches most
recitations of claim 1. Ans. 6—7 (providing citations to Otremba). The
Examiner finds that Otremba does not teach “a controller die is aligned with
and attached to said second metal clip, wherein said controller die is
monolithic integrated, mounted as a top die of the stack and is coupled to
both a first control node of said first power transistor and a second control
node of said second power transistor.” Id. at 7. The Examiner finds,
however, that Hinrichsmeyer and Saito teach claim 1 ’s recitations
concerning integration, the third die, and clip and that Ewe teaches using the
top die as a power die or controller die. Id. The Examiner concludes:
It would have been obvious to one of ordinary skill in the art at the
time the invention was made to use a three die stack arrangement
wherein the third die is a controller die which is aligned with and
attached to said second metal clip, wherein said controller die is
monolithic integrated, mounted as a top die of the stack and is coupled
to both a first control node of said first power transistor and a second
control node of said second power transistor, in the device of Otremba
et al. in order to reduce the size of the device by using conventional
stacked arrangement.
Id. at 7—8. Once again, a preponderance of the evidence supports the
Examiner’s findings and conclusion.
Appellants argue that the Examiner has failed to identify a technically
valid reason that would have prompted a person of ordinary skill in the art to
combine the prior art elements in the manner of claim 1. Appeal Br. 19.
The Examiner, however, provides detailed factual findings and technical
reasoning supporting the obviousness conclusion. Ans. 4—8, 11—16.
Appellants do not provide any persuasive arguments disputing the
Examiner’s findings of fact or disputing the Examiner’s reasoning. For
example, Appellants do not respond to the Examiner’s further explanation of
7
Appeal 2016-004109
Application 13/041,721
reasons to combine provided in the Answer. Ans. 11—16. On appeal, it is
Appellants’ burden to demonstrate harmful error in the appealed rejections,
and Appellants’ limited argument fails to meet that burden. See Ex parte
Yamaguchi, 88 USPQ2d 1606, 1614 (BPAI 2008) (on appeal, applicant must
show error by the Examiner); In re Chapman, 595 F.3d 1330, 1338 (Fed.
Cir. 2010), quoting Shinseki v. Sanders, 556 U.S. 396, 409 (2009) (“the
burden of showing that an error is harmful normally falls upon the party
attacking the agency’s determination.”).
Appellants also argue each reference individually. Appeal Br. 19.
For example, Appellants note that Hinrichsmeyer has a chip 19 in recess 15,
that Saito and Otremba do not teach a controller die, that Ewe shows a
power semiconductor device on large area contact regions 7. This
discussion of individual references fails to demonstrate error in the
Examiner’s conclusion that the combined teachings of the references would
have rendered the subject matter of claim 1 obvious. “Non-obviousness
cannot be established by attacking references individually where the
rejection is based upon the teachings of a combination of references.” In re
Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
Appellants also argue that none of the references teach a
“monolithically integrated control die and high-side power transistor.”
Appeal Br. 20. The Examiner, however, explains why the prior art teaches
this element (Ans. 18), and Appellants do not persuasively dispute the
Examiner’s findings.
DECISION
For the above reasons, we reverse the Examiner’s rejection of claims
1, 2, 6, and 11 as failing to satisfy the written description requirement of 35
8
Appeal 2016-004109
Application 13/041,721
U.S.C. § 112. We affirm the Examiner’s rejection of claims 1, 2, 6, and 11
as obvious over Hinrichsmeyer or Saito each in view of Ewe and Otremba
(rejection 2) and obvious over Otremba in view of Hinrichsmeyer, Saito, and
Ewe (rejection 3).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
9