Ex Parte Carlson

Patent Trial and Appeal Board

Nov 15, 2013

11044648 (P.T.A.B. Nov. 15, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte DAVID A. CARLSON
___________

Appeal 2011-005920
Application 11/044,648
Technology Center 2100
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Before JOSEPH L. DIXON, JEFFREY S. SMITH, and
DANIEL N. FISHMAN, Administrative Patent Judges.

FISHMAN, Administrative Patent Judge.

DECISION ON APPEAL

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Application 11/044,648

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This is an appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1-19. Br. 3. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
The Invention
Appellant’s invention relates to accelerated multiplication techniques
in a processor. Prior to issuing a sequence of multiply instructions for the
multiplication operation, a multiplier register in a multiply unit of the
processor is loaded with a multiplier value. The multiply unit stores
intermediate results of the multiplication operation in redundant format. The
intermediate results are shifted and stored in a product register of the
multiply unit so that carries between intermediate results are handled within
the multiply unit. See generally Abstract.
Claim 1, reproduced below, is illustrative with disputed limitations in
italics:
1. A processor comprising:
an instruction fetch unit including an instruction cache,
the instruction fetch unit fetching instructions associated with a
multiplication operation from the instruction cache;
an execution unit including a multiply unit and at least
one register file, the execution unit performing the
multiplication operation in the multiply unit based on the
fetched instructions;
the multiply unit including a multiplier register and a
product register; and
the at least one register file including a plurality of
general purpose registers for storing a multiplicand and a result
of a multiplication operation in the multiply unit; wherein a
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multiplier register load instruction loads the multiplier register
once with a multiplier value and clears the product register
prior to the start of the multiplication operation, the multiplier
value being stored in the multiplier register throughout the
multiplication operation, the multiplication operation including
a plurality of multiplication instructions, each multiplication
instruction being a single instruction that uses the stored
multiplier value and the multiplicand to produce an
intermediate result, and shifts and stores the shifted
intermediate result in the product register so that carries
between intermediate results are handled within the multiply
unit.

The Rejection
Claims 1-19 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Busaba (U.S. Patent Publication No. 2004/0230631 A1; published Nov.
18, 2004) and Strjbaek (U.S. Patent Publication No. 2002/0116432 A1;
published Aug. 22, 2002). Ans. 4-10.

Issues
Appellant’s arguments present us with the following issues:
1. Has the Examiner erred in finding that the combination of Busaba
and Strjbaek teaches “wherein a multiplier register load instruction
loads the multiplier register once with a multiplier value and clears
the product register prior to the start of the multiplication
operation, the multiplier value being stored in the multiplier
register throughout the multiplication operation” as recited in
claim 1?
2. Has the Examiner erred in combining Busaba and Strjbaek?
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ANALYSIS
Issue #1
The Examiner rejects claim 1 finding that Busaba teaches all
limitations but fails to disclose:
an instruction fetch unit including an instruction cache, the
instruction fetch unit fetching instructions associated with a
multiplication operation from the instruction cache: an
execution unit including a multiply unit and at least one register
file, the execution unit performing the multiplication operation
in the multiply unit based on the fetched instructions; and clear
the product register.
Ans. 4-5. The Examiner finds that Strjbaek discloses these features and
reasons that it would have been obvious to combine these teachings with
Busaba to “increase the system performance.” Ans. 5.
Appellant argues that Busaba “loads and updates its multiply register
at each cycle of the multiplication operation” and thus fails to teach loading
the multiplier register once before starting the multiplication operation and
fails to retain the multiplier value in the register throughout the operation.
Br. 8. We are unpersuaded. Busaba discloses two exemplary multiplication
operations using its multiplier circuits. A first example operation is
described in Busaba paragraphs 0051-0053 and Table 6 and a second
example is described in paragraphs 0054-0068 and Table 7. The Examiner
clarifies that Table 6 of the first example shows loading a multiplier register
(B3) with a multiplier value (m1) before starting the multiplication
operation. Ans. 11-12. As can be seen in Busaba Table 6 and its associated
description, register B3 retains the multiplier value throughout the
multiplication operation. The Examiner further clarifies that Table 7 of the
second example shows loading various registers (A1, B2, B3) with the
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multiplier value (mplier) before starting the multiplication operation. Ans.
12. As can be seen in Busaba Table 7 and its associated description, register
A1 retains the multiplier value throughout the multiplication operation.
Thus, we agree with the Examiner’s findings (Ans. 4, 11-12) that Busaba
teaches “a multiplier register load instruction loads the multiplier register
once with a multiplier value . . . the multiplier value being stored in the
multiplier register throughout the multiplication operation” as recited in
claim 1.
The Examiner relies on Strjbaek for showing, inter alia, clearing “the
product register prior to the start of the multiplication operation.” Ans. 5.
Appellant argues that Strjbaek’s ACX register “cannot be viewed as a
product register” and, regardless, further argues that Strjbaek fails to teach
clearing the ACX register prior to the multiplication operation. Br. 9. We
are unpersuaded. Appellant admits that the ACX register of Strjbaek “serves
as an additional register (i.e., in addition to the HI and LO registers) that is
used to provide 8 bits of additional integer precision beyond those provided
by the HI/LO register pair.” Br. 9. We agree. The Examiner explains that
the ACX register “is an extension precision register” (i.e., extending
precision of the product of the multiplication). Ans. 13. The HI/LO/ACX
registers of Strjbaek, in combination, provide the product result output of the
multiplier. See, e.g., Strjbaek ¶ 0035. Thus, by Appellant’s own admission
and as disclosed by Strjbaek, Strjbaek’s ACX register is clearly at least a
portion of a product—a product register as required by the claim whether or
not it contains the entire product result of the multiplication operation.
Further, Strjbaek states, “the MULTU instruction clears the ACX
register to all zeros.” Strjbaek, ¶ 0037. Although Appellant argues that the
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ACX is only cleared after completion of the operation (Br. 9), the Examiner
clarifies:
nothing in the secondary reference [Strjbaek] explicitly requires
clearing the ACX register to all zeros after the multiplication
operation, but rather the clearing must be done before the
multiplication operation wherein paragraph [0041] only details
the clearing ACX register after loading/moving/fetching data in
order to get ready for the multiplication since clearing the
register after multiplication would also wipe-out the result of
multiplication . . . .
Ans. 12-13. We agree. Clearly, the ACX register, which forms at least a
portion of a product, is cleared to zero prior to commencing a next
multiplication operation—i.e., cleared at the start of each operation.
In view of the above discussion, we are unpersuaded that the
Examiner erred in finding that the combination of Busaba and Strjbaek
teaches “wherein a multiplier register load instruction loads the multiplier
register once with a multiplier value and clears the product register prior to
the start of the multiplication operation, the multiplier value being stored in
the multiplier register throughout the multiplication operation” as recited in
claim 1.

Issue #2
Appellant argues:
Such a hypothetical system would require substantial
modification, effectively altering its principles of operation, to
behave in a manner defined by Applicant’s Claim 1.
Specifically, one would need to completely alter the
binary/cyclic approach of Busbaba [sic Busaba] and
significantly change the multiplication approach of Strjbaek to
make the hypothetical system act in a manner similar to that
recited in Applicant’s Claim 1. Even if the hypothetical system
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could be modified, the modification would only be done in
hindsight of Applicant’s disclosure and claims.
Br. 11. We are unpersuaded. The Examiner clarifies that both references
are in a related art (enhanced multiplier techniques) and “[n]othing in either
reference would explicitly exclude the combination of [the] other.” Ans. 15.
We agree. “[I]f a technique has been used to improve one device, and a
person of ordinary skill in the art would recognize that it would improve
similar devices in the same way, using the technique is obvious unless its
actual application is beyond his or her skill.” KSR Int’l Co. v. Teleflex Inc.,
550 U.S. 398, 417 (2007). Appellant has not provided sufficient, persuasive
evidence that a skilled artisan would be unable to combine the teachings of
the references to arrive at the claimed invention. Rather, we find that the
Examiner has articulated a reason for the combination based on rational
underpinnings, and we are therefore unpersuaded that the Examiner erred in
combining Busaba and Strjbaek.

For the reasons discussed above, we are not persuaded that the
Examiner erred in rejecting claim 1 and claims 2-19 not argued separately
with particularity. Br. 11-12.

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DECISION
For the above reasons, the Examiner’s decision to reject claims 1-19
under § 103 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2010).

AFFIRMED

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