Ex Parte Carballo et al

Board of Patent Appeals and Interferences

Jun 29, 2009

10289777 (B.P.A.I. Jun. 29, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte JUAN-ANTONIO CARBALLO, DAVID WILLIAM
BOERSTLER, and JEFFREY L. BURNS
_____________

Appeal 2009-002834
Application 10/289,777
Technology Center 2600
____________

Decided:1 June 29, 2009
____________

Before KENNETH W. HAIRSTON, MAHSHID D. SAADAT, and
THOMAS S. HAHN, Administrative Patent Judges.

HAIRSTON, Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from the Examiner’s final
rejection of claims 1 to 27. We have jurisdiction under 35 U.S.C. § 6(b).
We will sustain the rejections.
The Invention
Appellants’ invention is concerned with an interface transceiver for
interconnecting electronic devices, and particularly with an interface
transceiver which uses a logic state of an input signal to select a level of
complexity and power consumption. 2 Appellants’ claimed invention is
directed to a method and apparatus for controlling power consumption by
selecting a level of complexity in the circuitry of the transceiver.3
Claims 1 and 25, reproduced below, are representative of the subject
matter on appeal:
1. An interface transceiver for interconnecting electronic devices,
comprising:
at least one interface circuit having selectable power consumption,
and having an output terminal adapted for electrical connection to an
interface bus bearing one or more interface signals to a remote bus
interface receiver;
a select input coupled to said at least one interface circuit for
receiving a selection signal, whereby a level of complexity and power
consumption of said one or more interface circuits is selected by a
logic state of said select input.

2 See Abstract; Spec. 1, 3; claim 1.

3 See generally Spec. 1-3 and 5-7; claims 1 and 25.

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25. A method of controlling power consumption in an interface
transceiver, comprising:
providing at least one signal at an electrical output terminal of said
interface transceiver, wherein said output terminal is connected to an
interface bus that is remotely connected to a remote receiver;
receiving an indication of that power consumption of said interface
transceiver may be reduced; and
in response to said receiving, selecting a complexity of said
receiver.
The Applied Prior Art
The Examiner relies upon the following as evidence of
unpatentability:
Jenkins US 3,587,044 Jun. 22, 1971
Dickinson US 4,092,596 May 30, 1978
Nottingham US 4,803,638 Feb. 7, 1989
Lilley US 4,819,196 Apr. 4, 1989
Rogers US 5,016,269 May 14, 1991
Tam US 5,126,686 Jun. 30, 1992
Philips US 5,872,810 Feb. 16, 1999
Roberts US 5,880,837 Mar. 9, 1999
Takagi US 6,134,214 Oct. 17, 2000
Gillespie US 6,215,816 B1 Apr. 10, 2001
Kaewell US 6,243,399 B1 Jun. 5, 2001
Delp US 6,334,174 B1 Dec. 25, 2001
Mathe US 6,389,069 B1 May 14, 2002

The following twelve rejections are before us for review:
(i) Claims 1 to 3, 5, 6, 11, 15, 25, and 26 stand rejected under 35
U.S.C. § 103(a) as unpatentable over Gillespie and Mathe.4

4 We note that Appellants’ Brief states that the appeal includes all of the
finally rejected claims 1 to 27 (Br. 3), but that only claims 1 and 25 are to be
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(ii) Claims 4 and 14 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Tam.
(iii) Claims 7 and 16 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Lilley.
(iv) Claims 8 and 17 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Rogers.
(v) Claims 9 and 18 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Nottingham.
(vi) Claim 10 stands rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Takagi.
(vii) Claims 12, 19, and 27 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Roberts.
(viii) Claim 13 stands rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Dickinson.
(ix) Claims 20 and 22 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Philips.
(x) Claim 21 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Gillespie and Mathe, further in view of Delp.
(xi) Claim 23 stands rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Jenkins.
(xii) Claim 24 stands rejected under 35 U.S.C. § 103(a) as
unpatentable over Gillespie and Mathe, further in view of Kaewell.
We agree with Appellants that claims 1 and 25 are representative of

reviewed on appeal since all other claims on appeal depend from either
claim 1 or claim 25 (Br. 4). Appellants’ Notice of Appeal does not list the
claims appealed, and Appellants only present arguments as to claims 1 and
25 for purposes of this appeal (see Br. 4-9). No Reply Brief has been filed.
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the group of claims (claims 1 to 3, 5, 6, 11, 15, 25, and 26) which stand
rejected under 35 U.S.C. § 103(a) as unpatentable over Gillespie and Mathe.
The only ground of rejection presented in the instant appeal for review is the
rejection of claims 1 and 25 over Gillespie and Mathe. See 37 C.F.R.
§ 41.37(c)(1)(vi). Appellants do not present any arguments or request
review of the obviousness rejections (ii) through (xii) listed supra.
Arguments not made by Appellants in the Brief are considered waived. See
37 C.F.R. § 41.37(c)(1)(vii).
Appellants argue that Gillespie fails to teach an operational power
down mode or more than one operating mode, as set forth in each of
independent claims 1 and 25 (Br. 6-8). In other words, Appellants allege
that Gillespie only describes a single active operating mode and a single
(non-operational) power down mode (Br. 6). Appellants argue that the
Specification requires that complexity be selectable in multiple different
power level operational modes (Br. 7-8).

ISSUE
Based on Appellants’ arguments, the issue is: Have Appellants
demonstrated that the Examiner erred by finding that Gillespie and Mathe,
whether considered singly or in combination, teach (i) selecting “a level of
complexity and power consumption” as set forth in claim 1, and (ii) reducing
power consumption by “selecting a complexity” as set forth in claim 25?

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FINDINGS OF FACT
The record supports the following Findings of Fact (FF) by a
preponderance of the evidence:
Appellants’ Disclosure
1. As indicated supra, Appellants describe and claim an interface
transceiver 12A/12B for interconnecting electronic devices A/B
through an interface 10 (Fig. 1). The apparatus (see 20 in Fig. 2) and
method (see Fig. 4) select a level of complexity and power
consumption for one or more interface circuits 24 to 29 (see generally
Abstract; Figs. 1 and 2; claim 1) and reduce the power consumption of
the interface transceiver 12A/12B by selecting a complexity for a
remote receiver 14B (see Figs. 1 and 4; claim 25).
2. Appellants disclose that power consumption of the various circuits 24
to 29 is reduced by reducing the complexity of the circuits and can be
controlled by individual control bits (Spec. 8).
Gillespie
3. Gillespie describes an interface transceiver (Figs. 1, 2, 16) for
interconnecting electronic devices (see col. 1, ll. 13-36).
4. The interface device PHY includes at least one interface circuit (10
Mbps and 100 Mbps transmitters and receivers; see col. 1, ll. 39-62;
Fig. 1) having selectable power consumption (col. 1, ll. 51-52) and an
output terminal connected to an interface bus (RJ45C in Fig. 2).
5. The interface device PHY also includes a select input coupled to at
least one interface circuit for receiving a selection signal where the
logic state of the select input is used to select a level of complexity
and power consumption of the interface circuits (col. 3, ll. 45-67; cols.
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9-11, TABLE 2; the PDOWN bit selects a power mode which
determines the power consumption, the SPEED bit selects between
10Mbps and 100Mbps speeds which are proportional to a complexity,
and the DUPLEX bit selects between full duplex and half duplex
operational configurations which have differing complexities).
Mathe
6. Mathe, like both Gillespie and Appellants, describes an interface
transceiver (Fig. 1) that selects a level of complexity (col. 1, l. 55 to
col. 3, l. 15). More specifically, Mathe describes selecting a level of
complexity by using strategic programmable coefficients to control a
digital programmable filter in order to control power consumption
(see generally col. 1, ll. 16-52; col. 3, ll. 10-15; col. 4, ll. 20-23).
Mathe discloses that a selection can be made between a first
equalization filter and a second equalization filter in order to
determine the level of circuit complexity and power consumption (col.
3, ll. 10-15; col. 2, ll. 38-45).

PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 103, it is incumbent upon the
Examiner to establish a factual basis to support the legal conclusion of
obviousness. See In re Fine, 837 F.2d 1071, 1073 (Fed. Cir. 1988). The
Examiner’s articulated reasoning in the rejection must possess a rational
underpinning to support the legal conclusion of obviousness. In re Kahn,
441 F.3d 977, 988 (Fed. Cir. 2006).
The Examiner bears the initial burden of presenting a prima facie case
of obviousness, and Appellants have the burden of presenting a rebuttal to
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the prima facie case. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992).
Appellants have the burden on appeal to the Board to demonstrate error in
the Examiner’s position. See Kahn, 441 F.3d at 985-86.

ANALYSIS
Appellants have not particularly pointed out errors in the Examiner’s
reasoning to persuasively rebut the Examiner's prima facie case of
obviousness in the rejections of claims 4, 7 to 10, 12 to 14, 16 to 24, and 27.
As indicated infra, we hereby sustain the Examiner’s rejections of claims 4,
7 to 10, 12 to 14, 16 to 24, and 27 as being obvious under 35 U.S.C. § 103(a)
over Gillespie and Mathe in view of various tertiary references pro forma.
See 37 C.F.R. § 41.37(c)(1)(vii) (requiring a statement in the briefs as to
each ground of rejection presented by Appellant for review); 37 C.F.R. §
41.37(c)(1)(vii) (stating that arguments not presented in the briefs by
Appellant will be refused consideration); see also footnote 4 supra.
Turning now to the obviousness rejection of claims 1 to 3, 5, 6, 11,
15, 25, and 26 over Gillespie and Mathe, we agree with the Examiner’s
findings of fact and conclusions of obviousness with respect to claims 1 and
25 (Ans. 5-6, 18-20), and adopt them as our own, along with some
amplification of the Examiner’s explanation of the teachings of Gillespie
(see FF 3-5) and Mathe (see FF 6). See Fine, 837 F.2d at 1073; Kahn, 441
F.3d at 988. We will sustain the Examiner’s rejection of claims 1 to 3, 5, 6,
11, 15, 25, and 26 for the reasons that follow.
As indicated supra (FF 3-5), Gillespie describes all of the elements of
(i) claim 1 including a select input and logic state for selecting a level of
complexity and power consumption of at least one interface circuit, and (ii)
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claim 25 including reducing power consumption of the interface transceiver
by selecting the complexity of a receiver. In other words, claims 1 and 25
read in their entirety on Gillespie, whether considered alone or in
combination with Mathe, and the teachings of Mathe, are cumulative of what
is disclosed by Gillespie.5
The Examiner has provided articulated reasoning with a rational
underpinning to support the combination for the legal conclusion of
obviousness (Ans. 4-7, 18-20). See Kahn, 441 F.3d at 988. We agree with
the Examiner that both Gillespie and Mathe teach circuitry having a
selectable complexity (Ans. 20), and we find that Gillespie meets all of the
limitations of claims 1 and 25. Once the Examiner has satisfied the burden
of presenting a prima facie case of obviousness, the burden then shifts to
Appellants to present evidence and/or arguments that persuasively rebut the
Examiner's prima facie case. See Oetiker, 977 F.2d at 1445.
With regard to Appellants’ arguments (Br. 6-8) that Gillespie fails to
teach an operational power down mode, that Gillespie describes only one
operational mode, and that Appellants’ invention requires more than one
operational mode, these arguments are unpersuasive inasmuch as they are
not commensurate in scope with what is recited in claims 1 and 25.
Specifically, claims 1 and 25 do not recite an operational power down mode
or even require that the level of complexity or power consumption occur in a

5 “[A] lack of novelty in the claimed subject matter, e.g., as evidenced by a
complete disclosure of the invention in the prior art, is the ‘ultimate or
epitome of obviousness’” In re Fracalossi, 681 F.2d 792, 794 (C.C.P.A.
1982) (internal citation omitted). “[A] rejection for obviousness under § 103
can be based on a reference which happens to anticipate the claimed subject
matter.” In re Meyer, 599 F.2d 1026, 1031 (C.C.P.A. 1979).

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mode that is operational. The word “operation” and/or “operational” does
not occur in claims 1 or 25 (see claims 1 and 25).
With regard to Appellants’ arguments (Br. 7-8) that the Examiner
erred in combining Gillespie with Mathe due to a lack of motivation to
adjust complexity in Gillespie, this line of reasoning is unpersuasive since
Gillespie teaches selecting complexity (FF 5). Appellants’ argument (Br. 8)
that Gillespie and Mathe are not from the same field of endeavor, is
unconvincing in light of our findings that Appellants’ invention, Gillespie,
and Mathe all concern interface transceivers that select a level of complexity
and power consumption (FF 1, 4-6). Furthermore, Appellants’ contentions
(Br. 7-8) that the combination of Gillespie and Mathe is improper are moot
in view of our finding that Gillespie alone meets the limitations of claims 1
and 25.
In view of the foregoing, we will sustain the obviousness rejection of
claim 1 based upon the teachings of Gillespie and Mathe. The same holds
true for claim 25 which was argued with claim 1 (Br. 5-9). The obviousness
rejection of claims 2, 3, 5, 6, 11, 15, and 26 is sustained because Appellants
have not presented any patentability arguments for these claims apart from
the arguments presented for claims 1 and 25 (see Br. 5-9).

CONCLUSION OF LAW
Appellants have not shown that the Examiner erred in finding that
Gillespie with Mathe, whether singly or in combination, teaches (i) selecting
“a level of complexity and power consumption” as set forth in claim 1, and
(ii) reducing power consumption by “selecting a complexity” as set forth in
claim 25.
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As indicated supra, Appellants have presented no arguments with
respect to the rejections of claims 4, 7 to 10, 12 to 14, 16 to 24, and 27 as
being obvious under 35 U.S.C. § 103(a) over Gillespie and Mathe in view of
various tertiary references. As such, Appellants have not shown the
Examiner erred in rejecting these claims. See 37 C.F.R. § 41.37(c)(1)(vii).

ORDER
The decision of the Examiner to reject claims 1 to 27 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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