Ex Parte Camacho et al

Patent Trial and Appeal Board

Mar 8, 2016

12717335 (P.T.A.B. Mar. 8, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
121717,335 03/04/2010
112165 7590 03/10/2016
STATS ChipPAC/PATENTLAWGROUP:
Atkins and Associates, P.C.
55 N. Arizona Place, Suite 104
Chandler, AZ 85225
FIRST NAMED INVENTOR
Zigmund R. Camacho
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2515.0179 2575
EXAMINER
BOYLE, ABBIGALE A
ART UNIT PAPER NUMBER
2816
NOTIFICATION DATE DELIVERY MODE
03/10/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
main@plgaz.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ZIGMUND R. CAMACHO, DIOSCORO A. MERILO, and
LIONEL CHIEN HUI TAY 1
Appeal2014-004957
Application 12/717,335
Technology Center 2800
Before CHUNG K. PAK, CHRISTOPHER C. KENNEDY, and
JULIA HEANEY, Administrative Patent Judges.
KENNEDY, Administrative Patent Judge.
DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 15, 16, 18-28, and 32--41. We have jurisdiction under 35 U.S.C.
§ 6(b ).
We AFFIRM.
BACKGROUND
The subject matter on appeal relates to semiconductor devices and,
more particularly, to a package-on-package structure that is electrically
1 According to the Appellants, the real party in interest is ST ATS ChipP AC,
Ltd. Br. 1.
Appeal2014-004957
Application 12/717,335
interconnected by through-silicon vias ("TSV") formed in a wafer level chip
scale package ("WLCSP"). Spec. i-f 1; Claim 15. Claim 15 is reproduced
below from page 25 (Claims Appendix) of the Appeal Brief:
15. A method of making a semiconductor device, comprising:
providing a wafer level chip scale package (WLCSP) including
active devices and a first conductive layer formed over a first
surface of the WLCSP;
forming a conductive via through the WLCSP;
disposing a first semiconductor die over the WLCSP;
forming a first interconnect structure over the first conductive
layer; and
mounting a second semiconductor die in direct contact with the
first interconnect structure and electrically connected to the first
semiconductor die through the conductive via and WLCSP.
Additional claims appear in the Analysis section below.
EVIDENCE RELIED ON BY THE EXAMINER
Ference et al.
Hosomi
Kuan et al.
Kawabata et al.
US 6,225,699 B 1
US 2001/0028114 Al
US 7,553,752 B2
US 7,667,313 B2
REJECTIONS ON APPEAL
May 1, 2001
Oct. 11, 2001
June 30, 2009
Feb.23,2010
1. Claims 35-39 are rejected under 35 U.S.C. § 102(b) as
anticipated by Hosomi.
2. Claims 15, 16, 18-20, and 32-34 are rejected under 35 U.S.C.
§ 103(a) as unpatentable over Hosomi in view of Kuan and Ference.
3. Claims 21-28 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Kawabata in view of Ference.
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4. Claim 40 is rejected under 35 U.S.C. § 103(a) as unpatentable
over Hosomi in view of Kuan.
5. Claim 41 is rejected under 35 U.S.C. § 103(a) as unpatentable
over Kawabata in view of Kuan.
ANALYSIS
The Appellants present arguments only for claims 15, 21, and 3 5. We
select those claims as representative of the claims on appeal and limit our
discussion to those claims.
After review of the evidence in the appeal record and the opposing
positions of the Appellants and the Examiner, we determine that the
Appellants have not identified reversible error in the Examiner's rejections.
Accordingly, we affirm the rejections for reasons set forth by the Examiner
in the Final Action and in the Answer. See generally Final Act. 2-8;
Ans. 2-13. We add the following for emphasis and completeness.
Rejection 1
Claims 35-39 are rejected under 35 U.S.C. § 102(b) as anticipated by
Hosomi. Claim 35 is reproduced below from pages 28-29 (Claims
Appendix) of the Appeal Brief:
3 5. A method of making a semiconductor device, comprising:
providing a substrate including a first conductive layer formed
over a first surface of the substrate;
forming a conductive via through the substrate;
disposing a first semiconductor die over the substrate;
forming a first interconnect structure over the first conductive
layer; and
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Application 12/717,33S
mounting a second semiconductor die in contact with the first
interconnect structure and electrically connected to the first
semiconductor die through the conductive via and substrate.
Relying largely on Figure S of Hosomi, the Examiner finds that
Hosomi teaches each element of claim 3S. Final Act. 2-3. Concerning the
"mounting a second semiconductor die" limitation of claim 3S, the Examiner
finds that item 2 of Ho so mi Fig. S satisfies that element. Id.
The Appellants argue that Hosomi does not teach a second
semiconductor die "in contact with the first interconnect structure" because,
"[t]o be in contact, semiconductor chip S7B and electrode bump S9 need to
be on the same side of package substrate SOB. With package substrate SOB
disposed between semiconductor chip S7B and electrode bump S9,
semiconductor chip S7B is prevented from contacting electrode bump S9."
Br. 23.
Under the broadest reasonable claim interpretation consistent with the
Specification, we are not persuaded by the Appellants; argument. The
Appellants have pointed to nothing in the Specification that would limit the
plain meaning of "in contact with" as they have proposed. As the Examiner
explains, semiconductor chip S7B is "in contact with" electrode bumps S9
through other elements. Ans. 12-13; Hosomi Fig. S. Claim 3S, unlike, e.g.,
claim lS, does not require the second semiconductor die to be in "direct"
contact with the first interconnect structure; it requires only that it be "in
contact with" the first interconnect structure. Compare claim 3S with claim
lS; cf Seachange Int'!, Inc. v. C-COR, Inc., 413 F.3d 1361, 1369 (Fed. Cir.
200S) ("[T]here is ... a presumption that two independent claims have
different scope when different words or phrases are used in those claims.").
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Application 12/717,335
The Appellants' arguments do not persuade us that Hosomi Fig. 5 does not
teach such an arrangement.
Moreover, in the Answer the Examiner finds that, even if claim 35
were interpreted to require direct contact, Hosomi Fig. 5 teaches that. See
Ans. 12-13. The Appellants have not rebutted the Examiner's specific fact
findings concerning direct contact in Hosomi Fig. 5 and, therefore, provide
no basis to question the accuracy of those findings.
For those reasons, we affirm the Examiner's rejection of claim 35.
Because claims 36-39 depend from claim 35, and the Appellants present no
separate arguments for those claims, we likewise affirm the Examiner's
rejection of those claims.
Rejection 2
Claims 15, 16, 18-20, and 32-34 are rejected under 35 U.S.C.
§ 103(a) as unpatentable over Hosomi in view of Kuan and Ference. Claim
15 is reproduced above.
In the Final Action, the Examiner finds that Hosomi teaches each
element of claim 15 except (1) the use of a wafer level chip scale package
(WLCSP) as the substrate, and (2) "mounting a second semiconductor die in
direct contact with the first interconnect structure." Final Act. 4 (emphasis
added). The Examiner finds that Kuan teaches a similar method in which
the substrate is a WLCSP having active devices and conductive vias, and
that it would have been obvious to combine Kuan with Hosomi to "provide[]
a package allowing for higher integration of devices with differing
functionality while decreasing the package profile." Id. The Examiner finds
that Ference teaches a second semiconductor die in direct contact with an
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Application 12/717,335
interconnect structure, and that it would have been obvious to combine
Ference with Hosomi to "ma[k ]e more durable electrical connections." Id.
at 5.
In the Answer, the Examiner further finds that Hosomi does, in fact,
teach both (1) the use of a wafer level chip scale package (WLCSP) as the
substrate, and (2) "mounting a second semiconductor die in direct contact
with the first interconnect structure." Ans. 2--4, 12-13. Specifically,
referring to Figure 5 of Hosomi, the Examiner finds that "substrates 50a---c,
including active devices 57a and 57b, could be considered the WLCSP
including active devices," and that the second semiconductor is in direct
contact with the first interconnect structure when the term "first interconnect
structure" is broadly interpreted to include "bump 59, rear electrodes 55B,
connecting hole 50H, wiring layer 52b, wiring layer 54b, bump 58B, and
pad 57B." Id. at 2--4.
The Appellants present several arguments in opposition to the
Examiner's rejection, which we address in tum below:
1. The Appellants argue that Kuan's "wafer 50 [the WLCSP] does
not include active devices," as required by claim 15. Br. 11. We do not find
that argument persuasive because Kuan teaches that the "wafer structure 50
... incorporates a double-sided integration circuit 84. The double-sided
integration circuit 84 is an active integrated circuit device." Kuan at 6:7-9.
2. The Appellants argue that Kuan "does not teach or suggest forming
a conductive via through the WLCSP, disposing a first semiconductor die
over the WLCSP, or forming a first interconnect structure over the first
conductive layer." Br. 12. That argument is not persuasive because the
Examiner relies on Hosomi, not Kuan, for those features. See Final Act. 4.
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"[O]ne cannot show non-obviousness by attacking references individually
where, as here, the rejections are based on combinations of references." In
re Keller, 642 F.2d 413, 426 (CCPA 1981).
3. The Appellants argue that Kuan "does not teach or suggest
mounting a second semiconductor die in direct contact with the first
interconnect structure .... " Br. 12-13. That argument is not persuasive
because the Examiner relies on Ference for teaching direct contact. Final
Act. 5; see also Keller, 642 F.2d at 426. The Examiner likewise finds that
Hosomi teaches direct contact, Ans. 3--4, and the Appellants do not dispute
the Examiner's specific fact findings on that point.
4. The Appellants argue that Ference does not teach various features
of claim 15. Br. 13-14. That argument is not persuasive because the
Examiner relies on Ference for the teaching of direct contact; the Examiner
relies on Hosomi and Kuan for the other features, and the Appellants have
not argued that those features would not have been obvious in view of the
combination proposed by the Examiner. See Keller, 642 F .2d at 426.
5. The Appellants argue that "the proposed modification or
combination of the prior art would change the principle of operation of the
prior art." Br. 14--15. For instance, they argue that "[ m ]odifying the device
in Hosomi by forming chip-on-chip interconnections between the faces of
semiconductor chips 57S, as taught by Ference, would eliminate first wiring
layer 52A .... " Id. at 15. That argument is not persuasive. "The test for
obviousness is not whether the features of a secondary reference may be
bodily incorporated into the structure of the primary reference." Keller, 642
F.2d at 425. "Rather, the test is what the combined teachings of the
references would have suggested to those of ordinary skill in the art." Id.;
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see also In re Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983) ("[I]t is not
necessary that the inventions of the references be physically combinable to
render obvious the invention under review."). The Appellants' arguments,
which focus on bodily incorporation, fail to establish---or even to suggest-
that a person of ordinary skill in the art would not have been motivated to
combine (and capable of combining) Hosomi, Kuan, and Ference as
proposed by the Examiner. As the Examiner explains, "modifying packages
to include die with multiple sizes and electrical routing structures is well
known in the art, making the modification obvious to one of ordinary skill in
the art." Ans. 8. The Appellants' arguments do not persuade us that the
proposed modification involves anything more than ordinary skill and
creativity. See KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398, 418, 421 (2007).
* * *
For those reasons, we affirm the Examiner's rejection of claim 15.
Because claims 16, 18-20, and 32-34 depend from claim 15, and the
Appellants present no separate arguments for those claims, we likewise
affirm the Examiner's rejection of those claims.
Rejection 3
Claims 21-28 are rejected under 35 U.S.C. § 103(a) as unpatentable
over Kawabata in view of Ference. Claim 21 is reproduced below from
pages 26-27 (Claims Appendix) of the Appeal Brief:
21. A semiconductor device, comprising:
a substrate including a first conductive layer formed over a first
surface of the substrate;
a conductive via formed through the substrate;
a first semiconductor die disposed over the substrate;
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a first interconnect structure formed over the first conductive
layer; and
a second semiconductor die mounted in direct contact with the
first interconnect structure and electrically connected to the first
semiconductor component through the conductive via and
substrate.
The Examiner finds that Kawabata teaches each element of claim 21
except a second semiconductor die "in direct contact with" an interconnect
structure. Final Act. 6. As set forth above, the Examiner relies on Ference
for that feature and finds that a person of ordinary skill in the art would have
been motivated to incorporate that feature in Kawabata to achieve "more
durable electrical connections." Id. at 6-7.
The Appellants argue that Kawabata does not teach a second
semiconductor die in direct contact with the interconnect structure. Br. 16-
17. That argument is not persuasive because the Examiner relies on Ference
for that element, not Kawabata. See Keller, 642 F.2d at 426. Moreover, in
the Answer the Examiner finds that Kawabata does teach a second
semiconductor die in direct contact with the interconnect structure. Ans. 8-
9. The Appellants do not address the Examiner's specific findings of fact on
that point and, therefore, provide no basis for us to reject them.
The Appellants argue that Ference does not teach various features of
claim 21. Br. 1 7-18. That argument is not persuasive because the Examiner
relies on Ference for the teaching of direct contact; the Examiner relies on
Kawabata for the other features, and the Appellants have not argued that
those features would not have been obvious in view of the combination
proposed by the Examiner. See Keller, 642 F.2d at 426.
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As above, the Appellants argue that the proposed modification would
change the principle of operation of the prior art due to issues of bodily
incorporation. Br. 19--20 ("Modifying the device in Kawabata ... would
require removing second semiconductor substrate 451. ") We are not
persuaded by that argument for the reasons set forth above. The Appellants'
arguments do not persuade us that the proposed modification involves
anything more than ordinary skill and creativity. See KSR, 550 U.S. at 418,
421.
Accordingly, we affirm the Examiner's rejection of claim 21.
Because claims 22-2 8 depend from claim 21, and the Appellants present no
separate arguments for those claims, we likewise affirm the Examiner's
rejection of those claims.
Rejections 4 and 5
The Appellants present no separate arguments for claims 40 and 41,
which are subject to Rejections 4 and 5. Claims 40 and 41 depend from
claims 35 and 21, respectively, the rejections of which we have affirmed
above. Therefore, we likewise affirm the rejections of claims 40 and 41.
CONCLUSION
We AFFIRM the Examiner's rejections of claims 15, 16, 18-28, and
32--41.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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