Ex Parte Burghard et al

Patent Trial and Appeal Board

Jun 15, 2018

14812659 (P.T.A.B. Jun. 15, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/812,659 07/29/2015 Stephen John Burghard
134531 7590 06/19/2018
Cuenot, Forsythe & Kim, LLC
20283 State Road 7, Ste. 300
Boca Raton, FL 33498
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO.
GB920120135US3
8152-0255
CONFIRMATION NO.
8532
EXAMINER
AMOROSO, ANTHONY J
ART UNIT PAPER NUMBER
2113
NOTIFICATION DATE DELIVERY MODE
06/19/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ibmptomail@iplawpro.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte STEPHEN JOHN BURGHARD, DAVID J. HARMAN,
NEIL W. LEEDHAM, and ANDREW WRIGHT
Appeal 2018-001148
Application 14/812,659
Technology Center 2100
Before ALLEN R. MacDONALD, MICHAEL M. BARRY, and
MICHAEL J. ENGLE, Administrative Patent Judges.
BARRY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 26, 28-32, 34--38, and 40-43, which are all the pending claims. We
have jurisdiction under 35 U.S.C. § 6(b ).
We AFFIRM.
1 Appellants identify International Business Machines Corp. as the real party
in interest. App. Br. 1.
Appeal 2018-001148
Application 14/812,659
Introduction
Appellants' invention "relate[s] to diagnostic tracing of an executing
application." Spec. ,r 1. Appellants explain that for investigating computer
system problems, a copy of the data in the system's memory, commonly
referred to as core or dump data, can be stored for inspection. Id. ,r 2.
If the program under investigation has been written to
include trace entries, these can be enabled so that diagnostic
information in the form of trace data is written out or cut to a
trace file during the execution of the program. The
combination of the dump or core data and the trace data enables
engineers analyzing the performance of the relevant program to
inspect the contents of memory when the dump file was taken
and compare this with the trace data produced during the
processing of the program in an attempt to identify the cause of
a problem.
Id. ,I 3.
Claims 26, 32, and 38 are independent. Claim 26 is illustrative of the
claims on appeal:
26. A method of performing diagnostic tracing of an
executing application, comprising:
identifying a trace entry in trace data, the trace entry
including a pointer that refers to a memory address;
determining whether a value that is, or has been, stored at
the memory address is an erroneous value; and
indicating, responsive to the determination, the pointer as
being a suspicious value, wherein
the determining includes processing delta core data
generated for at least one trace entry, and
the delta core data represents at least a portion of a
difference between a first set of core data and a second set of
core data.
App. Br. 24 (Claims App'x).
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Application 14/812,659
Rejections
Claims 26, 28-32, 34--38, and 40-43 stand rejected as unpatentable on
the ground of nonstatutory double patenting over claims 1-6 of US
9,128,832 B2 (issued Sept. 8, 2015) and, alternatively, over claims 1-6 of
US 9,164,821 B2 (issued Oct. 20, 2015). Final Act. 3--4.
Claims 3 8 and 40-43 stand rejected as directed to a "computer
program product" that comprises a "computer-readable storage medium"
because "the claimed invention does not fall within one of the four
categories of patent eligible subject matter recited in 35 U.S.C. § 101."
Final Act. 4.
Claims 26, 28, 29, 32, 34, 35, 38, 40, and 41 stand rejected under pre-
AIA 35 U.S.C. § I02(b) as anticipated by Palus (US 2012/0066551 Al;
Mar. 15, 2012). Final Act. 7-9.
Claims 30, 31, 36, 37, 42, and 43 stand rejected under pre-AIA 35
U.S.C. § I03(a) as unpatentable over Paulus and Songer (US 7,080,283 Bl;
July 18, 2006). Final Act. 10-13.
ANALYSIS
The Board "reviews the obviousness rejection[ s] for error based upon
the issues identified by appellant, and in light of the arguments and evidence
produced thereon," and treats arguments not made as waived. Ex parte
Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential) (cited with
approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011)); see also
37 C.F.R. § 4I.37(c)(l)(iv).
Appellants do not argue the nonstatutory double patenting rejection of
claims 26, 28-32, 34--38, and 40-43; we summarily affirm that rejection.
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Application 14/812,659
§ 102(b) Rejection (Claim 26)
Appellants argue the Examiner errs in the anticipation rejection of
claim 26 because Palus fails to disclose "determining whether a value that is,
or has been, stored at the memory address is an erroneous value," as recited.
App. Br. 13-14; see also Reply Br. 2--4. We disagree. Palus discloses that
"[ e ]xamples of faults that may be detected" include "[ c ]hanges in data input
or output from the core that may be seen by changes in the core data trace
information." Palus ,r,r 15, 17. Artisans of ordinary skill would have
understood Palus therefore discloses detecting faults from changes in values
of the data from a core's memory and, more specifically, data stored an
address. See Palus ,r 10 ( explaining that the recorded trace information used
for fault detection includes addresses). A prior art reference need not use
identical language for there to be anticipation (i.e., an ipsissimis verbis or in
haec verbis test is not required). Whitserve, LLC v. Computer Packages,
Inc., 694 F.3d 10, 21 (Fed. Cir. 2012); Teva Pharm. Indus. Ltd. v.
AstraZeneca Pharms. LP, 661 F.3d 1378, 1384 (Fed. Cir. 2011) ("The prior
inventor does not need to .... conceive of its invention using the same
words as the patentee would later use to claim it."). Thus, Palus discloses
"determining whether a value that is, or has been, stored at the memory
address is an erroneous value," as recited.
Appellants also argue the Examiner errs in the rejection of claim 26
because Palus fails to disclose "indicating, responsive to the determination,
the pointer as being a suspicious value," as recited. App. Br. 14--15; see also
Reply Br. 4--5. Appellants specifically argue the Examiner fails to identify
disclosure of a pointer in the paragraphs cited in the rejection for this
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Application 14/812,659
limitation. App. Br. 14 (citing Palus ,r,r 15-17, 34). This argument is
unpersuasive.
As a threshold matter, we note the Examiner's finding for the recited
pointer is in the earlier recited limitation of "identifying a trace entry ...
including a pointer that refers to a memory address." Final Act. 7 ( citing
Palus ,r 46 ( disclosing trigger events from "executing from a particular
address, storing or fetching from a particular address," etc.)). Appellants do
not dispute this finding. We agree with the Examiner that this disclosure
from Palus would have disclosed identifying a pointer to a person of
ordinary skill in the art because artisans of ordinary skill would have
understood that a pointer is a data structure storing the address of other data
and that Pal us' s trace entries for trigger events based on address operations
specifically disclose trace entries that include pointers. As discussed above,
although anticipation requires disclosure, a prior art reference need not use
identical verbiage. Whitserve, 694 F .3d at 21.
Appellants contend, however, that determination of a fault by using
checksums in Palus does not disclose "indicating ... the pointer as being a
suspicious value" because "what kind of error is not indicated" and
"[t]herefore, Palus fails to identically disclose the limitations at issue."
Reply Br. 4. We disagree. By disclosing the use of a trace entry that is a
pointer that can trigger fault detection, Palus discloses indicating a fault
from a suspicious pointer, as recited. That Palus uses different wording than
"a suspicious value" is ofno import. Cf In re Bond, 910 F.2d 831, 832-33
(Fed. Cir. 1990) (citing Akzo N. V. v. US. Int'! Trade Comm 'n, 808 F.2d
1471, 1479 & n.11 (Fed. Cir. 1986)) (interpreting references "is not an
'ipsissimis verbis' test"); Standard Havens Prods., Inc. v. Gencor Indus.,
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Application 14/812,659
Inc., 953 F.2d 1360, 1369 (Fed. Cir. 1991) ("[a] reference ... need not
duplicate word for word what is in the claims"). Further, Appellants'
argument that Palus does not indicate "what kind of error" is not
commensurate with the scope of the claim. Reply Br. 4. We agree with the
Examiner that the limitation of "indicating ... the pointer as being a
suspicious value," as recited, reads on Palus's disclosure of determining a
fault due to a checksum mismatch identified from a trigger event from a
trace entry that is a pointer. Ans. 14.
Appellants further argue the Examiner errs in the rejection of claim 26
because Palus fails to disclose "the determining includes processing delta
core data generated for at least one trace entry" and "the delta core data
represents at least a portion of a difference between a first set of core data
and a second set of core data," as recited. App. Br. 15-18; see also Reply
Br. 5---6. This argument is unpersuasive.
Appellants define "core data" as "an image of data stored at a set of
memory locations at a particular point during execution of an application."
Spec. ,r 29. Consistent with this definition, ordinarily skilled artisans would
have understood Palus' s trace data, which includes data stored in memory
during application execution, to disclose "core data," as recited. See Palus
,r 17 (identifying use of "data input or output from the core" for detecting
faults based on changes in the data). Regarding "delta core data," such
artisans further would have understood that Palus's disclosure of trace data
for different points in application execution discloses processing different
sets of core data. See id. ,r 34 ("a sequence of trace data is ... provided to
CRC computation module 108 to form a checksum that is then compared to
the reference checksum"). Accordingly, Appellants do not persuade us the
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Examiner errs in finding that Palus, by generating different checksums for
comparison from trace data that includes multiple sets of core data, discloses
"the determining includes processing delta core data," as recited. Ans. 14--
15; see also Final Act. 7-8.
Appellants contend-
The checksums being different does not describe how the
underlying data is different as the checksums themselves are
calculated from the underlying data. For example, a checksum
of 1.5 compared to a checksum of 1.7 does nothing to explain
how the underlying data is different. The claimed invention
requires that "the delta core data represents at least of a portion
of a difference between a first set of core data and a second set
of core data" ( emphasis added).
Reply Br. 6; see also id. at 5 ( arguing the Examiner "fails to appreciate the
difference between 'a difference' and 'being different"'); App. Br. 16
("While Palus may determine whether a delta (between calculated checksum
and reference checksum) exists, this delta is not actually generated and then
processed. Instead, Palus merely compares one value to another."). This
argument is unpersuasive-as discussed supra, claim 26 broadly but
reasonably, in view of Appellants' Specification, reads on Palus' s
disclosure. Palus discloses detecting "[ c ]hanges" in the core data and
"comparing" checksums. Spec. ,r,r 15, 17, 34. In other words, under a
broadest reasonable interpretation, Palus discloses multiple sets of core data
within the trace data that are compared via checksums, and an ordinarily
skilled artisan would have understood such comparisons constitute
"processing delta core data" that "represents at least a portion of a difference
between a first set of core data and a second set of core data," as recited. As
discussed above, anticipation does not require that the prior art reference use
the same verbiage as the claim.
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Application 14/812,659
Appellants furthermore argue the Examiner errs in the rejection of
claim 26 because, in Palus, "non-matching checksums indicates a likelihood
of a 'system error"' but "the Examiner has not produced any evidence that a
'system error' necessarily (i.e., inherently) or explicitly refers to 'an
erroneous or suspicious value,' as alleged by the Examiner." App. Br. 18.
This argument is unpersuasive. As discussed supra, there is no ipsissimis
verbis requirement for anticipation, and an ordinarily skilled artisan would
have understood that trace data resulting in a checksum mismatch that
identifies a fault indeed discloses "an erroneous or suspicious value."
Accordingly, we sustain the 35 U.S.C. § 102(b) rejection of claim 26.
In doing so, we adopt the findings and reasons of the Examiner as set forth
in the Final Rejection and in the Answer. We also sustain the § 102(b)
rejection of claims 28, 29, 32, 34, 35, 38, 40, and 41, for which Appellants
offer no arguments separate from claim 26. App. Br. 13.
§ 103(a) Rejection (Claims 30 and 31)
Claim 30 recites "[t]he method of claim 26, wherein the determination
is based upon a declared data type of a data field stored within the memory
address." The Examiner finds that Songer, in view of Palus, teaches this
additional limitation. Final Act. 10-11 ( citing Pal us Abstract, ,r,r 11, 3 6, 46;
Songer Abstract, 4:30-36, 13:32--48). Appellants argue the Examiner errs
because Songer' s disclosure of "comparing trace data fields to high and low
values" as a trigger mechanism for when using trace data for tracing and
debugging "has nothing to do with determining whether a value stored at a
memory address is erroneous, as claimed." App. Br. 20
The Examiner, however, relies on Palus for disclosing "determining
whether a value that is, or has been, stored at a memory address is
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Application 14/812,659
erroneous." Final Act. 7. The Examiner finds the cited disclosure from
Songer's "system for providing simultaneous, real-time trace and debug of a
multiple processing core system" "in conjunction with generating triggers
used to create and analyze trace data as taught by Palus" renders obvious the
added limitations of claim 30. Final Act 10, 11 (specifically finding an
ordinarily skilled artisan would have been motivated to combine the
teachings of Pal us and Songer to "facilitate capturing simultaneous real-time
trace data from multiple processing cores and provide for the selective
collection, storage and analysis of the captured trace data" as taught by
Songer); see also Ans. 15-16. Given the argument in the Appeal Brief,
Appellants do not persuade us the Examiner fails to articulate reasoning
along with sufficient "rational underpinning to support the legal conclusion
of obviousness." In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006); see also
KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398,418 (2007) (quoting Kahn).
Appellants' argument that "[ o ]ne having ordinary skill in the art would have
used the information in Songer for the purpose stated by Songer - not for an
unrelated purpose (i.e., corresponding to that claimed)" (Reply Br. 7) is
conclusory and unpersuasive.
Accordingly, we sustain the 35 U.S.C. § 103(a) rejection of claim 30.
We also sustain the§ 103(a) rejection of claims 36 and 42, which Appellants
argue together with claim 30. App. Br. 19.
Claim 31 recites "[ t ]he method of claim 26, wherein the determination
is based upon a range of values expected for the value stored at the memory
address." The Examiner finds the same disclosure of Palus and Songer cited
in the rejection of claim 30 also teaches the added limitations of claim 31.
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Final Act. 11-13. Appellants again argue Songer fails to teach the recited
limitations. App. Br. 20-21.
The Examiner answers that-
Songer teaches trace data from a processing core being
segmented into various fields. A trace control state machine
contains a range mode bit for each field which, when enabled,
causes the corresponding segments of compare and mask
registers to behave as low-value and high-value registers,
respectively. These range mode bits can be used as a triggering
mechanism, and fields of the trace data are considered to be
matching when those trace data fields are between the low and
high values specified in the compare and mask registers,
respectively (Songer: Col. 13, Lines 32-48). This corresponds
to the expected range of values described in the claim.
Consequently, the presence of values in the trace data fields
which are outside the specified range would indicate an
erroneous value.
Ans. 16.
Appellants respond that the Examiner's finding that "the presence of
values in the trace data fields which are outside the specified range would
indicate an erroneous value" is conclusory. Reply Br. 8. Specifically,
Appellants' contend there is no indication in Songer that determining to
trigger based on a range for a value does not teach determining the value is
erroneous-"the range of Songer only identifies whether fields of the trace
data are 'matching' or not - not whether the fields are an 'erroneous value,'
as alleged." Id.
Appellants' arguments are unpersuasive because they read Songer too
narrowly. Triggers in Songer are used for debugging (see, e.g., Songer Title,
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Abstract, Background). The purpose of debugging is to identify errors. 2
Ordinarily skilled artisans would have understood that Songer' s setting of
triggers for debugging based on a range for the value of a trigger variable
teaches determining the value is erroneous "based upon a range of values
expected for the value," as recited.
Accordingly, we sustain the 35 U.S.C. § 103(a) rejection of claim 31.
We also sustain the§ 103(a) rejection of claims 37 and 43, which Appellants
argue together with claim 31. App. Br. 19.
§ 101 Rejection (Claims 38 and 4rJ-43)
Because we sustain the rejection of claims 38 and 40-43 under 35
U.S.C. §§ 102(b) and 103(a), their rejection under§ 101 is moot, and we
decline to opine on that rejection.
DECISION
For the above reasons-
we affirm the nonstatutory double patenting rejection of claims 26,
28-32, 34--38, and 40-43;
we affirm the pre-AIA 35 U.S.C. § 102(b) rejection of claims 26, 28,
29, 32, 34, 35, 38, 40, and 41; and
we affirm the pre-AIA 35 U.S.C. § 103(a) of claims 30, 31, 36, 37, 42,
and 43.
2 See, e.g., Merriam-Webster ( defining debug as "to eliminate errors in or
malfunctions of-debug a computer program") (www.merriam-webster.
com/dictionary/debug (last accessed June 13, 2018)).
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No time period for taking any subsequent action in connection with
this appeal maybe extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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