Ex Parte Bukris

Patent Trial and Appeal Board

Jul 22, 2014

12359761 (P.T.A.B. Jul. 22, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/359,761 01/26/2009 Moshe Bukris Bukris 1-M-USA 5020
46900 7590 07/23/2014
MENDELSOHN, DRUCKER, & DUNLEAVY, P.C.
1500 JOHN F. KENNEDY BLVD., SUITE 312
PHILADELPHIA, PA 19102
EXAMINER
KIM, KENNETH S
ART UNIT PAPER NUMBER
2111
MAIL DATE DELIVERY MODE
07/23/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MOSHE BUKRIS
____________

Appeal 2012-003563
Application 12/359,7611
Technology Center 2100
____________

Before FRED E. McKELVEY, HUNG H. BUI, and
TERRENCE W. McMILLIN, Administrative Patent Judges.

McMILLIN, Administrative Patent Judge.

DECISION ON APPEAL

This is a decision on appeal under 35 U.S.C. § 134(a) of the final
rejection of claims 1 and 3–20. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 According to Appellant, the real party in interest is Agere Systems, Inc. of
Allentown, Pennsylvania, which is a wholly-owned subsidiary of LSI
Corporation of Milpitas, California. (Appeal Br. 2).
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REJECTIONS ON APPEAL
(1) All pending claims (1 and 3–20) were rejected under 35 U.S.C.
§ 112, second paragraph, as being indefinite for failing to particularly point
out and distinctly claim the subject matter which Appellant regards as the
invention. Ans. 4–6.
(2) Claims 1, 3, 4, 9–14, 19, and 20 were rejected under 35 U.S.C.
§ 102(b) as being anticipated by U.S. Patent No. 6,920,549 B1 (July 19,
2005) (“Ukai”). Ans. 7–8.
(3) Claims 1, 3, 4, 9–14, 19, and 20 were rejected under 35 U.S.C.
§ 102(b) as being anticipated by U.S. Patent No. 5,875,324 (Feb. 23, 1999)
(“Tran”). Ans. 8-9.

DISCUSSION
The Claimed Invention
There are two pending independent claims. Independent claim 1 is a
device claim and independent claim 12 is a method claim. Appellant
canceled claim 2. Dependent claims 3–11 depend from device claim 1.
Dependent claims 13–20 depend from method claim 12. The language used
in the device and method claims is very similar and both the Appellant and
Examiner treat them the same. We shall do likewise.
Independent device claim 1 is representative and reads as follows:
1. A processor comprising:
a processing pipeline adapted to process a stream of
instructions received from an instruction cache (I-cache); and
a branch-target-buffer (BTB) circuit operatively coupled
to the processing pipeline and adapted to predict an outcome of
a branch instruction received via said stream based on
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branch-instruction information in the BTB circuit, wherein the
processor is adapted to:
perform an update of the branch-instruction
information in the BTB circuit based on processing the branch
instruction in the processing pipeline, said update being
performed after the processing pipeline has resolved a branch
condition corresponding to the branch instruction; and
initiate a pre-fetch from a main memory into the I-
cache of a branch-target instruction corresponding to the branch
instruction implicated in the update before a next entrance of
the branch instruction into the processing pipeline, wherein the
next entrance is an entrance that immediately follows an
entrance that triggered the update.

Appellant has not argued the dependent claims separately except to
note that claims 5–8 and 15–18 are only subject to the § 112 rejection
because they depend from rejected independent claims 1 and 12. Claims 5–
8 and claims 15–18 were not the subject of either prior art rejection. For this
reason, we consider all the claims together except as otherwise specifically
noted. 37 C.F.R. § 41.37(c)(1)(vii) (2010).

The Section 112 Rejection
The Examiner rejected all the pending claims as being indefinite
because it is unclear whether or not the “pre-fetch from a main memory in
the I-cache” recited in independent claims 1 and 12 occurs prior to the
“update of the branch-instruction information in the BTB circuit” or is
occurring subsequent as a separate second fetch. For example, in the Final
Office Action at 2, the Examiner said with regard to independent claims 1
and 12 that “it is not clear whether the target instruction is fetched after
resolution of the branch instruction and the initiated pre-fetch is meant to be
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for that fetch.” We agree that the claims are unclear in this regard and
therefore are indefinite.
The Supreme Court has recently interpreted the claim definiteness
requirement of 35 U.S.C. § 112 in Nautilus, Inc. v. Biosig Instruments, Inc.,
134 S. Ct. 2120 (2014). The Supreme Court said: “we read § 112, ¶2 to
require that a patent’s claims, viewed in light of the specification and
prosecution history, inform those skilled in the art about the scope of the
invention with reasonable certainty.” Nautilus, 134 S. Ct. at 2129. We do
not believe that the pending claims in this application meet the Nautilus
standard.
Appellant contends that the claims clearly set forth that the pre-fetch
occurs after the update. But, Appellant’s argument regarding the definition
of pre-fetch contradicts its argument regarding timing of the pre-fetch and
sequencing of the claim elements. For example, in the Reply Brief,2
Appellant argues that pre-fetch is a term of art that has a well-established
meaning of “retrieval of an instruction from the main memory into the cache
before the instruction is actually needed by the processor pipeline.”3 Reply
Br. 2 (emphasis omitted). We accept the Appellant’s proffered

2 Appellant’s argument in which it contends that pre-fetch is a term of art
with a well-established meaning was first presented in its Reply Brief.
Arguments made for the first time in a Reply Brief may not be given much
weight because the Examiner has no opportunity to address the new
arguments.
3 Appellant cites Wikipedia for this definition. Although we do not have to
accept Wikipedia as an authoritative source for technical definitions and
proof of established meaning to one of ordinary skill in the art, we will
consider the definition in this instance. We also note that Appellant failed to
make the required showing that this term had this well-established meaning
at the time the application was filed.
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interpretation of “pre-fetch.” However, the lack of clarity in the claims
arises because the update is “based on processing the branch instruction” and
is “performed after the processing pipeline has resolved a branch condition
corresponding to the branch instruction” and the pre-fetch is of the “branch
instruction implicated in the update.”
According to the Specification, a branch instruction is not fully
resolved until the branch instruction reaches the execute stage, 142E in
Figure 1 and 342E in Figure 3, near the end of the pipeline. Spec. 1:28–30.
In the drawings at Figures 1 and 3, the execute stage is the last step shown in
the processing pipeline, 140 in Figure 1 and 340 in Figure 3.
According to the well-established meaning of “pre-fetch” as advanced
by the Appellant, the branch instruction would be retrieved before it is
needed by the processor pipeline. Therefore, the “pre-fetch” would have to
occur before the branch instruction is processed and resolved. Nevertheless,
both these limitations are recited in the update step of the claims. It is thus
very unclear whether the “pre-fetch” occurs prior to the update or is an
additional fetch. In this regard, the Specification contradicts the claim
interpretation proffered by the Appellant and does not help to construe the
claims with reasonable certainty. The use of the term “pre-fetch” in
connection with a branch instruction that has already been subject to
processing in the pipeline and been resolved renders the claims very unclear.
During prosecution, the Appellant amended the claims in response to
the rejections. In the Amendment under 37 C.F.R. § 1.116 filed on May 2,
2011, in response to the Final Office Action, the Appellant amended both
independent claims 1 and 12 by adding the phrase “said update being
performed after the processing pipeline has resolved a branch condition
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corresponding to the branch instruction” to the update step and the phrase
“wherein the next entrance [of the branch instruction into the processing
pipeline] is an entrance that immediately follows an entrance that triggered
the update” to the pre-fetch step. The Examiner entered and considered
these amendments. See Advisory Action Before the Filing of an Appeal
Brief dated May 6, 2011. Among the remarks the Examiner made in this
Advisory Action were the following: “the amendment merely states what
[is] implicit in express terms” and “the claims as recited do not specifically
identify the order.” Advisory Action 2. We agree with these remarks. And,
unfortunately, these amendments appear to be contradictory to each other
with regard to the sequencing of the update step and the pre-fetch step and to
further contribute to the lack of clarity in the claims. The first of these
amendments makes explicit that the update occurs after the branch
instruction has been resolved, i.e., after the fetch and detect and execute
steps are completed. The second of these amendments contradicts the well-
established meaning proffered by the Appellant for the term pre-fetch. At
any rate, these amendments failed to make the claims clear.
The Specification of the application also expressly disavows reading
any particular sequencing of the method steps based upon the order of the
steps in the method claims. The Specification provides the following
disclaimer:
Although elements in the following method claims, if
any, are recited in a particular sequence with corresponding
labeling, unless the claim recitations otherwise imply a
particular sequence for implementing some or all of those
elements, those elements are not necessarily intended to be
limited to being implemented in that particular sequence.
Spec. 10:29–11:2.
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For these reasons, we affirm the rejection of all the pending claims
under 35 U.S.C. § 112, second paragraph, as being indefinite for failing to
particularly point out and distinctly claim the subject matter which Appellant
regards as the invention.

The Section 102 Rejections4
Claims 1, 3, 4, 9–14, 19, and 205 were rejected under 35 U.S.C.
§ 102(b) as being anticipated by both Ukai and Tran. In response to these
rejections, Appellant presented arguments limited to the sequencing of the
“update of the branch-instruction information” step and the “pre-fetch from
a main memory into the I-cache” step in its Appeal Brief and, as indicated
above, did not provide any arguments in response to the prior art rejections
with regard to the dependent claims. The dependent claims are argued by
Appellant to be novel based only upon the alleged novelty of independent
claims 1 and 12. We deem all other potential arguments in response to the
prior art rejections as being waived.
For purposes of considering the prior art rejections, we construe the
claims as interpreted by the Appellant with regard to the sequence of the
steps as discussed in the preceding section of this opinion. It is clear that the
Examiner also did so and the Appellant presented its arguments in response

4 Our decision to affirm the rejection of all the pending claims as indefinite
is sufficient to dispose of this appeal. We exercise our discretion to review
and affirm the prior art rejections. As indicated herein, in discussing these
rejections, we construe the claims as interpreted by the Appellant. Our use
of this construction should not be interpreted as indicating our agreement
with it or as any indication that the claims are not indefinite.
5 Claim 2 was canceled. Claims 5–8 and 15–18 were not the subject of any
prior art rejection.
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to the prior art rejections in accordance with these arguments. After
consideration of the prior art rejections, we consider these rejections to be
well-founded on the teachings of the cited prior art and we affirm the
rejections on these bases. As interpreted by the Appellant, the claims which
were the subject of the § 102 rejections are anticipated by both cited
references.
The Examiner’s Answer at 7 provides the following cites from Ukai
as teaching the “update of the branch-instruction information” step: column
1, line 47, column 2, line 51, column 7, lines 5–8 and 21, column 8, line 15,
and column 9, line 65, and the following cites from Ukai as teaching the
“pre-fetch from a main memory into the I-cache” step: column 1, lines 38
and 50, column 2, line 50, column 7, line 8, and column 9, line 65. We
agree that these cites from Ukai provide teachings of these elements as
found in the independent claims and in the sequence argued by the
Appellant.
The Examiner’s Answer at 8 provides the following cites from Tran
as teaching the “update of the branch-instruction information” step: column
2, line 20, column 10, lines 63 and 67, and column 11, lines 1, 26, and 35,
and the following cites form Tran as teaching the “pre-fetch from a main
memory into the I-cache” step: column 6, line 5, column 9, line 28, column
10, line 67, and column 11, line 41. We agree that these cites from Tran
provide teachings of these elements as found in the independent claims and
in the sequence argued by the Appellant.
Therefore, we affirm the rejections of claims 1, 3, 4, 9–14, 19, and 20
under 35 U.S.C. § 102(b) as being anticipated by Ukai and Tran.
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DECISION
The Examiner’s rejections under 35 U.S.C. §§ 102 and 112 are
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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