Ex Parte Buer

Patent Trial and Appeal Board

Sep 18, 2017

13783589 (P.T.A.B. Sep. 18, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/783,589 03/04/2013 Kenneth V. Buer 36956.06617/USM0091-US-2 8926
87364 7590 09/20/2017
Snell & Wilmer L.L.P (USMATasat)
Attn: John Platt
One Arizona Center
400 East Van Buren Street
Phoenix, AZ 85004-2202
EXAMINER
TRAN, PABLO N
ART UNIT PAPER NUMBER
2649
NOTIFICATION DATE DELIVERY MODE
09/20/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
jplatt@swlaw.com
IPDOCKET @ swlaw.com
stdavis @ swlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KENNETH V. BUER
Appeal 2017-005529
Application 13/7 83,5 891
Technology Center 2600
Before CARLA M. KRIVAK, HUNG H. BUI, and JON M. JURGOVAN,
Administrative Patent Judges.
BUI, Administrative Patent Judge.
DECISION ON APPEAL
Appellant seeks our review under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 1—5, 7—13, 16, and 19-25, which are
all the claims pending in the application. We have jurisdiction under
35 U.S.C. § 6(b).
We AFFIRM.2
1 According to Appellant, the real party in interest is ViaSat, Inc. App. Br.
1.
2 Our Decision refers to Appellant’s Appeal Brief (“App. Br.”) filed April
13, 2016; Reply Brief (“Reply Br.”) filed February 15, 2017; Examiner’s
Answer (“Ans.”) mailed December 15, 2016; Final Office Action (“Final
Act.”) mailed September 11, 2015; and original Specification (“Spec.”) filed
March 4, 2013.
Appeal 2017-005529
Application 13/783,589
STATEMENT OF THE CASE
Appellant’s invention relates to a compact high linearity monolithic
microwave integrated circuit (MMIC)-based resistive mixer including
“adjacent transistors, such as FETs (field effect transistors) [that] share
terminals,” thereby “reducing physical layout separation and
interconnections.” Spec. 12; Title; Abstract.
Claims 1 and 8 are independent. Claims 1 and 8 are reproduced
below with disputed limitations in italics:
1. A semiconductor device comprising:
a mixer comprising four mixing elements on a single
substrate,
wherein each mixing element of the four mixing elements
comprises two or more terminals within semiconductor portions
of the single substrate,
and wherein at least one terminal of a first mixing element
of the four mixing elements and at least one terminal of a second
mixing element of the four mixing elements are the same
terminal.
8. A semiconductor device comprising:
an integrated circuit including a mixer, wherein the mixer
comprises four field effect transistors, and
wherein the mixer has three or less total interconnect lines
coupling the four field effect transistors together.
App. Br. 29-32 (Claims App’x).
Examiner’s Rejection and References
Claims 1—5, 7—13, 16, and 19-25 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Villemazet et al. (US
2001/0046849 Al; published Nov. 29, 2001; “Villemazet”) and Gupta (US
6,163,877; issued Dec. 19, 2000). Final Act. 2—6.
2
Appeal 2017-005529
Application 13/783,589
ANALYSIS
Claims 1, 2, 4, 5, 7, 21, and 22
With respect to independent claim 1, the Examiner finds Villemazef s
high-frequency signal mixer, shown in Figure 1, teaches a mixer comprising
four mixing elements (transistors 2, 3, 4, and 5) on a single substrate, each
mixing element having two or more terminals within semiconductor portions
of the substrate, as claimed. Final Act. 2—3 (citing Villemazet Fig. 1).
Villemazef s Figure 1 is reproduced below with additional markings
for illustration.
Villemazef s Figure 1 shows a quad 1 for use in a high-frequency signal
mixer, including four transistors 2, 3, 4, and 5 disposed
in an “in-line” configuration in which transistors 2 and 3, and 4 and 5 are
each connected by their drain D, and transistors 3 and 4 are connected by
their source S. Villemazet || 17, 20.
3
Appeal 2017-005529
Application 13/783,589
To support the conclusion of obviousness, the Examiner relies on
Gupta for teaching the claimed two terminals of different mixing elements
being “the same terminal.” Final Act. 3 (citing Gupta Figs. 2, 3, and 6). In
particular, the Examiner finds Gupta discloses a terminal of one transistor,
and another terminal of an abutting transistor, are the “same/shared (no
interconnection) terminals.” Final Act. 3; Ans. 3 (citing Gupta 1:49—2:14).
The Examiner then reasons one of ordinary skill in the art would have
combined the drain terminals of Villemazef s transistors 2 and 3 to be the
same terminal with no interconnection wire therebetween, as taught by
Gupta, to reduce size and total interconnect length for Villemazet’s mixer
device. Ans. 3^4; Final Act. 3. Gupta’s Figures 2 and 3 are reproduced
below with additional markings for illustration.
204
V
\
6H
S TRANSISTOR
A" 204
0
TRANSISTOR
LAYOUT AS
ISA
REPRESENTATION
OF A LAYOUT
OF TRANSISTOR 204
ll«
Gupta’s Figure 2 illustrates a diffusion sharing technique
by which transistor layouts 203 and 205 (for transistors 202 and 204,
respectively) are placed to share a drain diffusion area. Gupta 1:50-61.
4
Appeal 2017-005529
Application 13/783,589
SCHEMATIC 106
REPRESENTS THE
THXIMESTOR OF
SCHEMATIC 602
AETES. FOLDING
INFO TWO LEGS
OR FOLDS
Jw, WE*_____aOfc
TAYOE'T 300 ;S A
LAYOUT OF
S'! ML 'E A ; !C 3L6
LAYOUT M0 IS
AHOTHER POSSIBLE
LAYOUT OF
SCHEMATIC 300
Gupta’s Figure 3 illustrates a transistor folding technique by which a
transistor 302 is converted into smaller, multiple transistors (e.g., the two
transistors shown in schematic 306 and layout 308) called folds, or legs,
which are connected in parallel and placed together on a semiconductor
chip. Gupta 2:1—16, 3, 26—27.
Appellant disputes the Examiner’s factual findings regarding Gupta.
Appellant acknowledges Gupta teaches “two [transistor] layouts can be
abutted to each other so that a diffusion area is shared.” App. Br. 12.
However, Appellant contends “each transistor [of Gupta] is illustrated to
have its own distinct Source terminal and Drain terminal, and those
terminals, at most, are illustrated next to, or having a common boundary
with, another similar separate terminal,” all terminals therefore being
“separate and distinct from one another.” App. Br. 12—13 (citing Gupta
2:13, Figs. 3, 6). Thus, Appellant argues Gupta’s “‘abutting’ does not make
the terminals the ‘same’ terminal” as recited in claim 1 because “abutting”
5
Appeal 2017-005529
Application 13/783,589
merely means “next to, or having a common boundary with, another similar
separate terminal.” App. Br. 12—13 (citing www.dictionary.com and
www.merrian-webster.com); Reply Br. 3 (citing Gupta 2:13, 4:29).
Appellant additionally disputes the Examiner’s rationale for combining the
references. App. Br. 14—15. Particularly, Appellant argues the Examiner’s
combination of Villemazet and Gupta lacks articulated reasoning, and would
render Villemazet inoperable for its intended purpose. App. Br. 14—17;
Reply Br. 6—7.
We do not find Appellant’s arguments persuasive. Instead, we find
the Examiner has provided a comprehensive response to Appellant’s
arguments supported by a preponderance of evidence. Ans. 3—6. As such,
we adopt the Examiner’s findings and explanations provided therein. Id. At
the outset, we note claim terms are given their broadest reasonable
interpretation consistent with the Specification. In re Am. Acad, of Sci. Tech
Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). Under the broadest reasonable
interpretation, claim terms are given their ordinary and customary meaning,
as would be understood by one of ordinary skill in the art in the context of
the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
(Fed. Cir. 2007).
Appellant’s Specification does not provide an explicit and exclusive
definition of the claimed term “same terminal.” In fact, Appellant’s
Specification does not mention the term “same terminal.” Rather,
Appellant’s Specification describes examples of “shared” terminals as
follows:
In one exemplary embodiment, at least one of the source
terminal, drain terminal and gate terminal are shared among a
plurality of adjacent three terminal semiconductor portions.
6
Appeal 2017-005529
Application 13/783,589
In one exemplary embodiment, at least one of the source
terminal, drain terminal and gate terminal may be shared
among a plurality of adjacent three terminal semiconductor
portions.
Referring now to Figure 2, an exemplary MMIC
implemented FET resistive mixer 200 is illustrated. In this
orientation, the components of adjacent FETs (e.g. source
and/or drain) may be “shared. ”
In one exemplary embodiment and with reference to
Figure 4, a circuit layout of a MMIC based FET resistive mixer
200 in accordance with various exemplary embodiments of the
present invention is provided. In this embodiment, the sharing
of the plurality of three terminal semiconductor portions is
depicted. In this exemplary embodiment, there are no
interconnect line lengths associated with the RF+ signal, 260,
RF- signal 265 and IF+ signal 250 as all are integral to the
MMIC. Similarly, in this exemplary embodiment, there are no
interconnect line lengths associated with drain 240, source 222,
and drain 242 as all are directly coupled to and/or integral to the
MMIC.
[A]t least one of the emitter terminal, collector terminal
and base terminal are shared among a plurality of adjacent
three terminal semiconductor portions.
\A\djacent transistors, such as FETs (field effect
transistors) share terminals reducing physical layout separation
and interconnections.
Spec. 7, 10, 21, 45, 50, Abstract (emphases added).
Based on Appellant’s Specification, the Examiner has broadly
interpreted the claimed terminals being “the same terminal” as
encompassing Gupta’s terminals that share a diffusion area. Ans. 3^4 (citing
Gupta 1:49-2:14, Figs. 2 and 3). We find the Examiner’s interpretation
7
Appeal 2017-005529
Application 13/783,589
reasonable and consistent with Appellant’s Specification, which describes
“adjacent” transistors “sharing” terminals. See Spec. ]Hf 7, 10, 21, 45, 50,
Abstract. Gupta similarly describes terminals that are shared between
abutting transistors that share a diffusion area. See Gupta 1:49-2:14, 5:52—
57 (“Terminals Y and Z are shared between [transistors] Nl, N2, and N3,
respectively.”).
Thus, Gupta’s shared terminals—shared between abutting transistors
that share a diffusion area—are commensurate with terminals (of different
mixing elements) that “are the same terminal” as claimed and with the broad
description of such terminals in Appellant’s Specification.
We are also not persuaded by Appellant’s arguments that the
Examiner’s combination of Villemazet and Gupta relies on a modification
that would render Villemazet inoperable. App. Br. 14—17. Particularly,
Appellant argues a combination of Villemazet and Gupta would have “the
Sources of [Villemazet’s] four FETs (FET2-FET5)... all tied together” like
the Sources of Gupta’s Figure 6, which “would be the equivalent of tying
[Villemazet’s] RF/2 and RF together,” thereby (1) “causing] the sources of
FET2-FET5 to all receive the same signal” and (2) causing Villemazet’s
circuit to “not operate as intended to cancel the unwanted frequencies.”
App. Br. 16—17. Appellant’s argument is also not persuasive because the
rejection put forth by the Examiner does not require all sources of
Villemazet’s four FETs to be tied together. That is, although Gupta’s Figure
6 illustrates transistors connected in parallel (i.e., with all sources tied
together, and all drains tied together), Gupta’s shared-terminal technology
does not require abutting transistors to be connected in parallel. See Gupta
Fig. 2, Fig. 7 (illustrating transistors Nl, N2, N3 connected in series and
8
Appeal 2017-005529
Application 13/783,589
sharing terminals Y and Z), 5:50-57. Rather, Gupta discloses two
transistors “can be abutted” so “they share the drain [or source] diffusion
area.” See Gupta 1:59—61, 2:13—16.
In view of Gupta’s teaching of shared terminals without
interconnection wires therebetween, we agree with the Examiner that one of
ordinary skill in the art would have modified Villemazet “to combine the
drain terminals of transistors 2 & 3, source terminals of transistors 3 & 4,
and drain terminals of transistors 4 & 5 to become the same or shared
terminals, respectively, . . . by [] utilizing Gupta[sic] teaching in order to
reduce size” and “reduce total interconnect length.” Ans. 3^4; Final Act. 3.
This modification does not render Villemazet inoperable because the
modification does not change the electrical connections between
Villemazef s transistor terminals and RF signals’ ports.
Accordingly, Appellant’s arguments have not persuaded us of error in
the Examiner’s rejection of claim 1. Thus, we sustain the Examiner’s
rejection of claim 1, and dependent claims 2, 4, 5, 7, 21, and 22, which
Appellant does not argue separately. App. Br. 13, 17.
Claims 8—10
With respect to independent claim 8, the Examiner finds one of
ordinary skill in the art would have modified Villemazef s device—based on
Gupta’s diffusion sharing technique—to share the drain terminals of
transistors 2 and 3 with no interconnect lines therebetween, share the source
terminals of transistors 3 and 4 with no interconnect lines therebetween, and
share the drain terminals of transistors 4 and 5 with no interconnect lines
therebetween, as discussed supra with respect to claim 1. Final Act. 3; Ans.
4. The Examiner then finds Villemazef s device, thus modified to
9
Appeal 2017-005529
Application 13/783,589
incorporate Gupta’s diffusion sharing technique, would have only three total
interconnect lines coupling the four field effect transistors together, thus
teaching the limitation of claim 8. Final Act. 3; Ans. 4. These three
interconnect lines coupling Villemazef s four field effect transistors together
include: (1) the line connecting the gates (G) of transistors 2 and 4 at Vgl,
(2) the line connecting the gates (G) of transistors 3 and 5 at Vg2, and (3) the
line connecting the sources (S) of transistors 2 and 5 at RF/2. Ans. 4 (citing
Villemazet Fig. 1).
Appellant contends Villemazef s device as modified to incorporate
Gupta’s diffusion sharing technique would still have “6 interconnect lines”
because the combination of Villemazet and Gupta “would result in
implementing each transistor of Villemazet as multiple parallel transistors,
but not changing the interconnects” between Villemazef s transistors. Reply
Br. 8, 11 (emphasis added); see also App. Br. 19, 22—24.
As discussed supra with respect to claim 1, we are not persuaded that
Gupta’s shared-terminal technology requires adjacent transistors to be
connected in parallel. Additionally, as discussed supra with respect to claim
1, we agree with the Examiner that the combination of Villemazet and Gupta
teaches a mixer device in which (1) drain terminals of transistors 2 and 3 are
the same terminal, (2) source terminals of transistors 3 and 4 are the same
terminal, and (3) drain terminals of transistors 4 and 5 are the same terminal,
such that “there remain[] only three interconnect lines” that “couple the four
transistors together.” Ans. 4.
Appellant additionally contends the Examiner’s combination of
Villemazet and Gupta lacks articulated reasoning, and would render
Villemazet inoperable for its intended purpose. App. Br. 21—24. However,
10
Appeal 2017-005529
Application 13/783,589
as discussed supra with respect to claim 1, we agree with the Examiner that
the combination of Villemazet and Gupta would advantageously reduce
device size and total interconnect length without rendering Villemazet
inoperable.
Accordingly, Appellant’s arguments have not persuaded us of error in
the Examiner’s rejection of claim 8. Thus, we sustain the Examiner’s
rejection of claim 8, and dependent claims 9 and 10, which Appellant does
not argue separately. App. Br. 19, 24.
Dependent claims 3 and 11
With regard to dependent claims 3 and 11 argued separately—and
reciting “three total interconnect lines,” or “three or less total interconnect
lines”—Appellant reiterates the same arguments as for claim 8. App. Br.
19—20. Appellant further argues claim 3 based on its dependency from
claim 1. Thus, for the same reasons as claims 1 and 8, we sustain the
Examiner’s rejection of claims 3 and 11.
Dependent claims 13, 16, and 23
With regard to dependent claims 13 and 23 argued separately—and
reciting terminals being “shared” or “the same terminal”—Appellant
reiterates the same arguments as for claim l’s “same terminal” limitation.
App. Br. 13—14. Appellant further argues claims 13 and 23 based on their
dependency from claim 8. Thus, for the same reasons as claims 1 and 8, we
sustain the Examiner’s rejection of claims 13 and 23.
Appellant argues dependent claim 16 based on its dependency from
claim 8. Appellant further restates the claim language of the claim 16 and
asserts the recited limitations are not found in the prior art. App. Br. 20;
Reply Br. 8—9. Such assertions are merely attorney arguments and not
11
Appeal 2017-005529
Application 13/783,589
substantive arguments of Examiner error. See 37 C.F.R. § 41.37(c)(l)(iv)
(2013); see also In reLovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011). Thus,
for the same reasons as claims 8, we sustain the rejection of dependent claim
16.
Dependent Claim 12
Dependent claim 12 recites that “a longest interconnect line of the
three total interconnect lines is no more than 100 microns.” The Examiner
takes Official Notice that this limitation is taught by the prior art because,
although “Villemazet and Gupta do not explicitly disclose[] such teaching of
interconnect line length of the three total interconnect lines is no more than
100 microns,” “such is notoriously well known in the art.” Final Act. 4.
Appellant argues the Examiner’s Official Notice is improper because
Appellant has adequately traversed the Official Notice and the Examiner has
not provided any documentary evidence in return. App. Br. 20—21. In the
Answer, the Examiner provides documentary evidence to demonstrate the
claimed feature is well known in the art, including Crafts (US 5,610,429;
issued Mar. 11, 1997), Booske et al. (US 5,672,541; issued Sept. 30, 1997;
“Booske”), Colwell et al. (US 5,698,873; issued Dec. 16, 1997; “Colwell
‘873”), and Colwell et al. (US 5,691,218; issued Nov. 25, 1997; “Colwell
‘218”). Ans. 4—5.
In the Reply Brief, Appellant then argues the cited documentary
evidence fails to demonstrate the limitation of claim 12 is capable of instant
and unquestionable demonstration as being well-known. Reply Br. 9—11.
We also are not persuaded by Appellant’s argument. Rather, we agree with
the Examiner that limiting the longest interconnect line to no more than 100
microns in a semiconductor device is common knowledge in the
12
Appeal 2017-005529
Application 13/783,589
semiconductor art. Such is evidenced by Colwell ‘873 which discloses a
base cell for, e.g., a RAM circuit, the base cell including multiple transistors
connected by interconnect lines, and the “single base cell includ[ing] 15 grid
points (21 pm) in the X direction and 8 grid points (11.20 pm) in the Y
direction.” See Colwell ‘873, 6:8—10, 46-63, Abstract, Figs. 2 and 3a; Ans.
4. That is, since the base cell’s dimensions are 21 pm in the X direction and
11.20 pm in the Y direction, the longest interconnect line in Colwell’s base
cell is less than 100 pm (microns).
Thus, we agree with the Examiner that semiconductor devices with
the longest interconnect line of 100 microns or less are common knowledge
and well-known in the art, and therefore sustain the Examiner’s rejection of
claim 12.
Dependent Claims 19, 20, 24, and 25
Dependent claim 19 recites “the two or more terminals of each mixing
element [of claim 1 ] collectively comprise a plurality of lines extending in
parallel in a first direction,” and claim 24 recites “the source and drain
terminals of each field effect transistor [of claim 23] collectively comprise a
plurality of lines extending in parallel in a first direction.” Dependent claims
20 and 25 further require the gate terminals to extend in the same first
direction and between adjacent lines of the plurality of lines.
Appellant contends “[t]he references combined do not disclose
anything about the orientation of all the terminals of all four FETS.” Reply
Br. 14; see also App. Br. 25—27. We are not persuaded by Appellant’s
argument because Gupta discloses all terminals of its transistors are
fabricated as lines extending in parallel in the same direction, as shown in
Gupta’s Figures 2-4. Final Act. 5—6 (citing Gupta Figs. 2—8); Ans. 5—6.
13
Appeal 2017-005529
Application 13/783,589
Thus, Gupta evidences that aligning all transistor terminals (sources, drains,
and gates) in parallel along the same direction is a known circuit fabrication
technique. We therefore agree with the Examiner that it would have been
obvious, from Gupta’s disclosure, to align all terminals (sources, drains, and
gates) of Villemazet’s transistors in parallel along the same direction, with
the gates between adjacent sources and drains as shown in Gupta. See Gupta
Figs. 2-4. As Appellant’s arguments have not persuaded us of error in the
Examiner’s rejection of claims 19, 20, 24, and 25, we sustain the Examiner’s
rejection of claims 19, 20, 24, and 25.
CONCLUSION
On the record before us, we conclude Appellant has not demonstrated
the Examiner erred in rejecting claims 1—5, 7—13, 16, and 19-25 under
35U.S.C. § 103(a).
DECISION
As such, we AFFIRM the Examiner’s Final Rejection of claims 1—5,
7-13, 16, and 19-25.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
14