Ex Parte Bu et al

Board of Patent Appeals and Interferences

Jun 22, 2009

11372430 (B.P.A.I. Jun. 22, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte HAOWEN BU, BRIAN HORNUNG, P. R. CHIDAMBARAM,
AMITABH JAIN, RAJESH KHAMANKAR, NANDU MAHALINGAM,
and SRINIVANSAN CHAKRAVARTHI
____________________

Appeal 2009-001621
Application 11/372,4301
Technology Center 2800
____________________

Decided:2 June 22, 2009
____________________

Before MAHSHID D. SAADAT, MARC S. HOFF, and CARLA M.
KRIVAK, Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL

1 The real party in interest is Texas Instruments Incorporated.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
Appeal 2009-001621
Application 11/372,430

STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 11-18.3 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appellants’ invention relates to complementary metal oxide
semiconductor (CMOS) transistor formation. Appellants form lightly-doped
extension regions adjacent each transistor gate stack; form a layer of
insulating material over the lightly-doped extension regions; and form an
interfacial layer of nitrogen at the interface of the insulating layer and the
lightly-doped extension regions. Appellants then form source and drain
regions in the semiconductor substrate; form a capping layer of contiguous
silicon nitride over the substrate and each of the gate stacks; anneal, with the
capping layer in place, the extension and source and drain regions; and
remove the capping layer after the annealing step (Spec. 3).
Claim 11 is exemplary:
11. A semiconductor structure formed in the process of fabricating a
CMOS transistor structure prior to an activating anneal, comprising:
a semiconductor substrate having an P-type dopant region to support
an NMOS transistor of the CMOS transistor structure and a N-type dopant
region to support a PMOS transistor of the CMOS transistor structure, each
of the N-type dopant and P-type dopant regions having an overlying gate
stack including a conductive gate structure and a dielectric gate structure;
lightly-doped extension regions in the semiconductor substrate
adjacent each gate stack;
a layer of insulating material over a total exposed surface of the
lightly-doped extension regions;
an interfacial layer of nitrogen formed at the interface of the lighted-
doped extension regions and the layer of insulating material;

3 Claims 1-10 have been canceled.
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source and drain regions in the semiconductor substrate adjacent to
each of the gate stacks; and
a capping layer of contiguous silicon nitride over the semiconductor
substrate and each of the gate stacks of the CMOS transistor structure.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Guo US 6,878,583 B2 Apr. 12, 2005

Claims 11, 12, 16, and 17 stand rejected under 35 U.S.C. § 102(e) as
being anticipated by Guo.
Claims 13-15 and 18 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Guo.
Throughout this decision, we make reference to the Appeal Brief
(“Br.,” filed October 3, 2007) and the Examiner’s Answer (“Ans.,” mailed
December 20, 2007) for their respective details.
ISSUES
Appellants argue that Guo does not teach a layer of insulating
material, composed of silicon oxide, over a total exposed surface of the
lightly-doped extension regions, nor an interfacial layer of nitrogen formed
at the interface of the lightly-doped extension regions and the layer of
insulating material, nor a capping layer of contiguous silicon nitride having a
thickness of 200-1000 angstroms, nor a gate stack having a nitride sidewall
deposited with a BTBAS precursor.
Appellants further argue that it would not have been obvious to
modify Guo to include a dopant concentration for the extension regions, or
the source and drain regions, in the range of about 1-2 e20 atoms/cm3, nor to
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include an interfacial nitride layer with an atomic nitrogen concentration in
the range of 2-15 atomic percent.
Appellants’ arguments present us with the following issues:
1. Have Appellants shown that the Examiner erred in finding that
Guo teaches: a layer of insulating material, composed of silicon oxide, over
a total exposed surface of the lightly-doped extension regions; an interfacial
layer of nitrogen formed at the interface of the lightly-doped extension
regions and the layer of insulating material; a capping layer of contiguous
silicon nitride having a thickness of 200-1000 angstroms; or a gate stack
having a nitride sidewall deposited with a BTBAS precursor, as the claims
require?
2. Have Appellants shown that the Examiner erred in finding that
it would have been obvious to modify Guo to provide extension regions and
source and drain regions with the dopant concentration claimed, or that the
interfacial nitride layer should have an atomic nitrogen concentration in the
range of 2-15 atomic percent?

FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
The Invention
1. According to Appellant, the invention concerns complementary
metal oxide semiconductor (CMOS) transistor formation (Spec. 3).
Guo
2. Guo teaches an integration method to enhance gate activation in
a CMOS device (col. 1, ll. 8-10).
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3. Guo teaches dielectric spacers 16, made of an insulating
material, that overlay a total exposed surface of the lightly-doped extension
regions 18 (col. 3, ll. 25-26; Fig. 4).
4. The dielectric spacers are composed of silicon oxide (col. 3, ll.
25-26).
5. Guo teaches that the oxide of dielectric spacer 16, including the
portion at the interface of the lightly-doped extension regions and the
remaining insulating material, is subjected to thermal nitridation in a
nitrogen-containing atmosphere (col. 3, ll. 30-33; Fig. 1).
6. Guo teaches that the thickness of cap dielectric film 22 is kept
to approximately between 100 Å to 500 Å (col. 4, ll. 6-8). The cap dielectric
film may be formed of silicon dioxide (col. 4, l. 4).
PRINCIPLES OF LAW
“A rejection for anticipation under section 102 requires that each and
every limitation of the claimed invention be disclosed in a single prior art
reference.” See In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007)
(quoting In re Paulsen, 30 F.3d 1475, 1478-79 (Fed. Cir. 1994)).
Anticipation of a claim requires a finding that the claim at issue reads on a
prior art reference. Atlas Powder Co. v. IRECO, Inc., 190 F.3d 1342, 1346
(Fed. Cir. 1999) (quoting Titanium Metals Corp. v. Banner, 778 F.2d 775,
781 (Fed. Cir. 1985)).
On the issue of obviousness, the Supreme Court has stated that “the
obviousness analysis cannot be confined by a formalistic conception of the
words teaching, suggestion, and motivation.” KSR Int’l Co. v. Teleflex Inc.,
550 U.S. 398, 419 (2007). Further, the Court stated “[t]he combination of
familiar elements according to known methods is likely to be obvious when
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it does no more than yield predictable results.” Id. at 416. “One of the ways
in which a patent’s subject matter can be proved obvious is by noting that
there existed at the time of the invention a known problem for which there
was an obvious solution encompassed by the patent’s claims.” Id. at 419-
420.
“[W]here the general conditions of a claim are disclosed in the prior
art, it is not inventive to discover the optimum or workable ranges by routine
experimentation.” In re Aller, 220 F.2d 454, 456 (CCPA 1955). “[R]outine
experimentation within the teachings of the art is not patentable, even
though some improvement may be obtained thereby.” In re Fay, 347 F.2d
597, 600 (CCPA 1965)(internal citations omitted). A particular parameter
must first be recognized as a result-effective variable, i.e., a variable which
achieves a recognized result, before the determination of the optimum or
workable ranges of said variable might be characterized as routine
experimentation. In re Antonie, 559 F.2d 618, 620 (CCPA 1977).
“[I]t is the patentability of the product claimed and not of the recited process
steps which must be established.” In re Brown, 459 F.2d 531, 535 (CCPA
1972). “[E]ven though product-by-process claims are limited by and defined
by the process, determination of patentability is based on the product itself.”
In re Thorpe, 777 F.2d 695, 697 (Fed. Cir. 1985). “Where a product-by-
process claim is rejected over a prior art product that appears to be identical,
although produced by a different process, the burden is upon the applicant to
come forward with evidence establishing an unobvious difference between
the claimed product and the prior art product.” In re Marosi, 710 F.2d 799,
803 (Fed. Cir. 1983).
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ANALYSIS
CLAIM 11
Appellants argue that Guo does not anticipate claim 11 because Guo
fails to teach a layer of insulating material over the total exposed surface of
the lightly-doped extension regions; Guo fails to teach an interfacial layer of
nitrogen formed at the interface; and Guo’s gate element 14 cannot
simultaneously meet the conductive gate structure of the gate stack, the
interfacial layer of nitrogen, and the spacer sidewalls (Br. 12-13). We do not
find Appellants’ arguments persuasive of Examiner error.
Guo teaches dielectric spacers 16, made of an insulating material, that
overlay a total exposed surface of the lightly-doped extension regions 18 (FF
3). Guo, thus, teaches the “layer of insulating material” recited.
We concur in the Examiner’s finding that Guo teaches the claimed
interfacial layer of nitrogen (Ans. 5). Guo teaches that the oxide of dielectric
spacer 16, including the portion at the interface of the lightly-doped
extension regions and the rest of the insulating material, is subjected to
thermal nitridation in a nitrogen-containing atmosphere (FF 5), which will
result in the presence of nitrogen at the interface (Ans. 11). We further
concur in the Examiner’s finding that the annealing process will inherently
result in the formation of a nitrogen interfacial layer (Ans. 11). Therefore,
we find that Guo teaches the claimed interfacial layer of (i.e., containing)
nitrogen formed at the interface of the lightly-doped extension regions 18
and the layer of insulating material 16.
Finally, Appellants’ argument that conductor gate 14 of Guo cannot
simultaneously meet three elements of the claimed invention is not germane
to the rejection at issue, because the Examiner does not rely on conductor
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gate 14 to teach those limitations. We further observe that, contrary to
Appellants’ argument, “spacer sidewalls” are not recited in claim 11.
Therefore, because Appellants have not established error in the
Examiner’s position, we will sustain the Examiner’s rejection of claim 11
under 35 U.S.C. § 102.
CLAIM 12
Appellants argue that Guo fails to anticipate the subject matter of
claim 12 because Guo does not teach a silicon oxide insulating layer,
pointing out that Guo’s capping layer 22 is made of silicon nitride (Br. 15).
Appellants’ argument is not persuasive of Examiner error. Guo
teaches dielectric spacers 16 that are positioned so as to cover the total
exposed surface of the lightly-doped extension regions (FF 3). The dielectric
spacers are composed of silicon oxide (FF 4).
Therefore, because Appellants have not identified error in the
Examiner’s position, we will sustain the Examiner’s rejection of claim 12
under 35 U.S.C. § 102.
CLAIM 16
Appellants argue that Guo does not teach the claimed thickness of the
silicon nitride capping layer, because the language of claim 16, relied upon
by the Examiner, only specifies a thickness for a silicon dioxide capping
layer (Br. 16).
Appellants’ argument is not persuasive of Examiner error. Guo
teaches that the thickness of cap dielectric film 22 is kept to approximately
between 100 Å to 500 Å (FF 6). Guo’s teaching of thickness is not restricted
to one particular material; Guo teaches that the cap dielectric film may be
formed of silicon dioxide (FF 6).
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Therefore, because Appellants have not identified error in the
Examiner’s position, we will sustain the Examiner’s rejection of claim 16
under 35 U.S.C. § 102.
CLAIM 17
Appellants argue that Guo does not anticipate claim 17 because Guo
does not specify a nitride sidewall deposited with a BTBAS precursor.
Appellants’ argument is not persuasive, because, as the Examiner notes, the
gate stack of Guo includes a nitride sidewall (Fig. 4, element 16). In
Appellants’ view, because BTBAS includes a carbon-containing compound
that affects transistor performance, one of ordinary skill would not have
considered using a BTBAS precursor “unless it is proactively specified” (Br.
17).
Appellants’ argument is not persuasive. The Examiner rejected this
product-by-process claim over a prior art product that appears to be
identical. The burden then shifted to Appellants to come forward with
evidence establishing an unobvious difference between the claimed product
and the prior art product. Marosi, 710 F.2d at 803. Appellants’ argument
regarding the use of BTBAS precursor amounts to an argument that one of
ordinary skill in the art would not have practiced the same process as
Appellants. It is not an argument that the claimed product differs in an
unobvious way from the prior art product. Appellants have not presented any
evidence tending to establish that difference.
Because Appellants did not demonstrate error in the Examiner’s
rejection of claim 17 under § 102, we will sustain the rejection.
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CLAIM 13
Appellants argue that Guo does not render the claimed invention
obvious, because Guo does not teach that the extension regions for the
PMOS transistors have a dopant concentration in the range of about 1-2 e20
atoms/cm3, and that such a dopant concentration is not “notoriously well
known in the art,” as the Examiner found (Br. 18).
Appellants’ arguments are not persuasive of Examiner error. We agree
with the Examiner that Appellants have disclosed no criticality to or
unexpected results flowing from the particular range of dopant concentration
claimed (Ans. 14). We further agree with the Examiner that dopant
concentrations corresponding to “lightly-doped” are well known in the art
(Ans. 6), and that determining the optimum range of dopant concentration
here would require no more than routine experimentation. See Aller, 220
F.2d at 456.
Accordingly, we conclude that Appellants have not demonstrated
error in the Examiner’s rejection, and we will sustain the § 103 rejection of
claim 13.
CLAIM 14
Appellants argue that Guo does not render the claimed invention
obvious, because Guo does not teach that the source and drain regions for
the PMOS transistors have a dopant concentration in the range of about 1-2
e20 atoms/cm3, and that such a dopant concentration is not “notoriously
well known in the art,” as the Examiner found (Br. 19).
Appellants’ arguments are not persuasive of Examiner error. We agree
with the Examiner that Appellants have disclosed no criticality to or
unexpected results flowing from the particular range of dopant concentration
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claimed (Ans. 14). We further agree with the Examiner that appropriate
dopant concentrations for source and drain regions are well known in the art
(Ans. 6), and that determining the optimum range of dopant concentration
here would require no more than routine experimentation. See Aller, 220
F.2d at 456.
Accordingly, we conclude that Appellants have not demonstrated
error in the Examiner’s rejection, and we will sustain the § 103 rejection of
claim 14.
CLAIM 15
Appellants argue that Guo does not render the claimed invention
obvious. Specifically, because Guo allegedly does not teach the interfacial
nitride layer recited in parent claim 11, Guo therefore also does not teach the
claimed concentration range of atomic nitrogen (Br. 20).
This argument is not considered persuasive, because as noted supra,
we find that Guo does teach the interfacial nitride layer recited in claim 11.
In the absence of any separate argument for the patentability of claim 15,
then, we do not find error in the Examiner’s rejection of claim 15 under
§ 103, for the same reasons expressed with respect to the § 102 rejection of
claim 11, supra.
CLAIM 18
Appellants present the same arguments for the various elements of
claim 18 (i.e., that Guo does not teach a layer of silicon oxide over the total
exposed surface of the lightly-doped extension regions; that Guo does not
teach an interfacial layer of nitrogen; that elements 14 and 16 of Guo cannot
anticipate all of the conductive structure of the gate stack, the oxide
sidewall, and the interfacial layer of nitrogen; and that Guo does not teach a
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capping layer of silicon nitride of the appropriate thickness) that were
presented in favor of the patentability of claims 11 and 16. As noted supra,
we find that Guo teaches all of the elements of claims 11 and 16. We
therefore find that Guo teaches all of the analogous elements of claim 18.
Accordingly, we will sustain the § 103 rejection of claim 18 for the same
reasons given supra for sustaining the § 102 rejection of claims 11 and 16.
CONCLUSIONS OF LAW
1. Appellants have not shown that the Examiner erred in finding
that Guo teaches: a layer of insulating material, composed of silicon oxide,
over a total exposed surface of the lightly-doped extension regions; an
interfacial layer of nitrogen formed at the interface of the lightly-doped
extension regions and the layer of insulating material; a capping layer of
contiguous silicon nitride having a thickness of 200-1000 angstroms; and a
gate stack having a nitride sidewall deposited with a BTBAS precursor, as
the claims require.
2. Appellants have not shown that the Examiner erred in finding
that it would have been obvious to modify Guo to provide extension regions
and source and drain regions with the dopant concentration claimed, or that
the interfacial nitride layer should have an atomic nitrogen concentration in
the range of 2-15 atomic percent.
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ORDER
The Examiner’s rejection of claims 11-18 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD

TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS, TX 75265
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