Ex Parte Brundridge et al

Patent Trial and Appeal Board

Oct 16, 2012

11122614 (P.T.A.B. Oct. 16, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte MICHAEL A. BRUNDRIDGE, PAUL T. ARTMAN,
BRYAN KRUEGER, and ABHISHEK MEHTA
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Appeal 2010-005805
Application 11/122,614
Technology Center 2100
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Before DEBRA K. STEPHENS, KALYAN K. DESHPANDE, and
LARRY J. HUME, Administrative Patent Judges.

HUME, Administrative Patent Judge.

DECISION ON APPEAL

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Application 11/122,614

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This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection
of claims 1-21. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
STATEMENT OF THE CASE 1
The Invention
“The present disclosure relates in general to information handling
systems, and more particularly to a system and method for indirect throttling
of a system resource by a processor.” (Spec. p. 1, ll. 2-5 (“TECHNICAL
FIELD”)).
Exemplary Claims
Claims 1 and 9 are exemplary claims which are reproduced below
(emphasis added to disputed limitations):
1. An information handling system, comprising:
a chassis operable to receive modular components;
a processor disposed in the chassis;
a system resource in communication with the processor; and
a management module associated with the chassis, the
management module operable to generate a throttle signal that
throttles operation of the processor in response to receiving an
alarm;

1 Throughout this Decision, we refer to the Final Office Action (FOA)
mailed Aug. 28, 2008; the Appeal Brief (App. Br.) filed Dec. 23, 2008; the
Examiner’s Answer (Ans.) mailed Mar. 20, 2009; the Reply Brief (Reply
Br.) filed May 19, 2009; and the original Specification (Spec.) filed May 5,
2005.
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wherein throttling operation of the processor reduces
throughput of the system resource.

9. A method for indirect throttling of a system resource by a
processor, comprising:
receiving a throttle signal at a processor disposed in a chassis if
a management module associated with the chassis receives an
alarm, the throttle signal operable to throttle operation of the
processor; and
reducing throughput of a system resource in communication
with the processor in response to receiving the throttle signal.
Prior Art
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Shaffer US 2003/0084088 A1 May 1, 2003
Appellants’ Admitted Prior Art (AAPA) – Spec, p. 3, ll. 4-14.
Rejections on Appeal 2
A. The Examiner has rejected claims 9-11, 14, and 15 under 35
U.S.C. § 102(b) as being anticipated by Shaffer (Ans. 4).
B. The Examiner has rejected claims 1-8, 12, 13, and 16-21 under
35 U.S.C § 103(a) as being unpatentable over Shaffer in view of AAPA
(Ans. 6).

2 Appellants have argued in both the Appeal Brief and Reply Brief (e.g., see
Reply 2-3) that the Examiner improperly failed to enter an Amendment after
Final Rejection. We note that such matters are petitionable and not
appealable, and we do not consider these arguments further in reaching our
Decision.
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GROUPING OF CLAIMS
Based upon Appellants’ arguments against the rejections (App. Br. 5-
8), we select the following representative claims to decide this appeal in
accordance with those arguments and rejections:
Claim 1: Claims 1-8, 12, 13, and 16-21 stand or fall together with
claim 1. (See App. Br. 6-8).
Claim 9: Claims 9-11, 14, and 15 stand or fall together with claim
9 (See App. Br. 5-6).
We have only considered those arguments raised by Appellants in the
Briefs. Arguments Appellants could have made but chose not to make in the
Briefs have not been considered and are deemed to be waived.
PRINCIPLES OF LAW
When it is necessary to select elements of various teachings in order
to form the claimed invention, we ascertain whether there is any suggestion
or motivation in the prior art to make the selection made by applicant.
Interconnect Planning Corp. v. Feil, 774 F.2d 1132, 1143 (Fed. Cir. 1985).
In KSR, the Court held the following:
Often, it will be necessary for a court to look to interrelated
teachings of multiple patents; the effects of demands known
to the design community or present in the marketplace; and
the background knowledge possessed by a person having
ordinary skill in the art, all in order to determine whether
there was an apparent reason to combine the known
elements in the fashion claimed by the patent at issue. To
facilitate review, this analysis should be made explicit. See
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In re Kahn, 441 F. 3d 977, 988 (C.A. Fed. 2006)
(“[R]ejections on obviousness grounds cannot be sustained
by mere conclusory statements; instead, there must be some
articulated reasoning with some rational underpinning to
support the legal conclusion of obviousness”). As our
precedents make clear, however, the analysis need not seek
out precise teachings directed to the specific subject matter
of the challenged claim, for a court can take account of the
inferences and creative steps that a person of ordinary skill
in the art would employ.
KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
ISSUES AND ANALYSIS
1. 35 U.S.C. § 102(b): Claims 9-11, 14, and 15
Appellants’ Contentions
Appellants assert their claimed invention is not anticipated by Shaffer.
Specifically, Appellants contend that “Shaffer fails to disclose, either
expressly or inherently, ‘receiving a throttle signal at a processor disposed in
a chassis if a management module associated with the chassis receives an
alarm, the throttle signal operable to throttle operation of the processor’ and
‘reducing throughput of a system resource in communication with the
processor in response to receiving the throttle signal[,]’ as recited in Claim
9.” (App. Br. 5).
Further in this regard, Appellants also contend that “the cited portion
of Shaffer [i.e., Shaffer at ¶ [0038]] at most discloses throttling or reducing
the throughput of a processor . . . [but] does not disclose ‘reducing
throughput of a system resource in communication with the processor[,]’ as
recited in Claim 9.” (App. Br. 6).
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Issue 1
Did the Examiner err in finding that Shaffer discloses “receiving a
throttle signal at a processor disposed in a chassis if a management module
associated with the chassis receives an alarm, the throttle signal operable to
throttle operation of the processor,” and “reducing throughput of a system
resource in communication with the processor in response to receiving the
throttle signal,” as recited by claim 9?
Analysis
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner has erred. We disagree with Appellants’
conclusions with respect to claim 9, and we adopt as our own (1) the
findings and reasons set forth by the Examiner in the action from which this
appeal is taken and (2) the reasons and rebuttals set forth by the Examiner in
the Examiner’s Answer (Ans. 5-6 and 14-15) in response to Appellants’
Arguments (App. Br. 5-6; Reply 3-5).
In particular, we concur with the Examiner’s finding that Appellants’
Specification discloses that “[e]ach processor 60 that receives the throttle
signal reduces its operating speed . . . ,” (Ans. 15, citing Spec. at p. 28, ll. 2-
4) and “system resources . . . may be indirectly throttled by processors 60
because processors 60 reduce the frequency with which they request and
receive information.” (Ans. 15, citing Spec. at p. 28, ll. 8-11).
We agree with the Examiner that although the claims are not limited
by this description in the Specification, “[i]t is clear from the Specification
that ‘reducing throughput of a system resource in communication with the
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processor’ is done by throttling or reducing the throughput of a processor.”
(Ans. 15). As such, the Examiner’s observation regarding Appellants’
disclosure and the teachings of Shaffer are not inconsistent in this regard.
We also agree with the Examiner’s finding that
Shaffer discloses each of the carriers include a plurality of
resources such as computer processors and memory
resources to facilitate the performance of task (see page 2
paragraph 22), indicating the communication of resources
with a processor. Similar to appellant’s Specification,
Schaffer further discloses throttling or reducing the
throughput of a processor or processor type resource (see
page 5 paragraph 38 lines 1-7). If instructions of the
processor are provided at a reduced rate, the communication
between the processor and the other resource(s) would be
reduced, indicating a reduced throughput of a system
resource in communication with the processor in response to
receiving the throttle signal.
Ans. 15.
Thus, we find that Shaffer discloses throttling or reducing the
throughput of a processor. Additionally, such throttling in response to
receiving a throttle signal would result in reduced throughput of a system
resource in communication with the processor.
With respect to the recitation of “. . . if a management module
associated with the chassis receives an alarm,”3 the term “alarm”

3 We point out to the Examiner that if further prosecution of the application
is pursued, the conditional phrase “if a management module associated with
the chassis receives an alarm” implies that the associated method step is not
performed if the stated condition is not met, such that the method step need
not be performed in all situations.
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encompasses Shaffer’s temperature threshold functionality (e.g., see Shaffer
at ¶¶ [0023] and [0035]). (Ans. 14). Appellants have not set forth any
additional evidence or rationale to demonstrate that the Examiner’s
construction of “alarm” is unreasonably broad or inconsistent with the
Specification.
Further in this regard, we agree with the Examiner that
Shaffer discloses decreasing the instruction throttling if the
temperature of the carrier is above a threshold (see page 5
paragraph 38). Examiner has interpreted identifying the
temperature of the carrier being above the threshold as
reading on the limitation “alarm operable to indicate failure
of one of the modular component”. It is understood in order
for one to identify the temperature of the carrier is above a
threshold, a signal or alarm must be present.
Ans. 17.
Accordingly, Appellants have not convinced us of any error in the
Examiner’s characterization of the cited art and related claim construction.
We therefore agree with the Examiner that Shaffer discloses the limitations
“receiving a throttle signal at a processor disposed in a chassis if a
management module associated with the chassis receives an alarm, the
throttle signal operable to throttle operation of the processor,” and “reducing
throughput of a system resource in communication with the processor in
response to receiving the throttle signal,” as recited by claim 9.
Therefore, we sustain the Examiner’s rejection of claims 9-11, 14, and
15.
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2. 35 U.S.C. § 103(a): Claims 1-8, 12, 13, and 16-21
Appellants’ Contentions
Appellants assert their claimed invention is not obvious over Shaffer
in view of AAPA. (App. Br. 6-8). Specifically, Appellants contend that
“Shaffer, either alone or in combination with AAPA fails to disclose, teach or
suggest, ‘throttling operation of the processor reduces throughput of the
system resource’ as recited in Claims 1 and 16.” (App. Br. 6, 7).
Appellants additionally contend that
A premise of the Examiner's rejections of Claims 1 and 16 is
that Shaffer discloses at Paragraph [0038] “throttling
operation of the processor reduces throughput of the system
resource.” (Final Office Action, Pages 16 and 20).
However, for reasons analogous to those set forth above
with respect to Claim 9, Appellants submit that Shaffer fails
to disclose a “throttling operation of the processor reduces
throughput of the system resource” as recited in Claims 1
and 16. Accordingly, Shaffer in combination with AAPA
fails to disclose each and every limitation of Claims 1 and
16, and thus, cannot render obvious Claims 1 and 16.
App. Br. 7.
Appellants further contend that neither Shaffer nor AAPA, either
alone or in combination, teaches or suggests an alarm operable to indicate
either a failure of one of the modular components or removal of one of the
modular components from the chassis. (App. Br. 6, 8). Similarly,
Appellants contend that “neither Shaffer nor AAPA teach or suggest an
alarm.” (Reply Br. 6).
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Finally, Appellants contend that “the Examiner has unduly interpreted
the term ‘failure’ recited in the pending Claims,” and that “the ‘failure’
recited is not merely just an ‘overheating of devices’ as the Examiner
contends.” (Reply Br. 5).
Issue 2
Did the Examiner err in finding that the combination of Shaffer and
AAPA teaches or suggests “a management module . . . operable to generate
a throttle signal that throttles operation of the processor in response to
receiving an alarm; wherein throttling operation of the processor reduces
throughput of the system resource,” as recited by claim 1?
Analysis
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner has erred. We disagree with Appellants’
conclusions with respect to claims 1-8, 12, 13, and 16-21, and we adopt as
our own (1) the findings and reasons set forth by the Examiner in the action
from which this appeal is taken and (2) the reasons and rebuttals set forth by
the Examiner in the Examiner’s Answer (Ans. 6-7) in response to
Appellants’ Arguments (App. Br. 6-8, 16-18; Reply Br. 5-6).
We concur with the conclusions reached by the Examiner, particularly
the Examiner’s findings that the combination of Shaffer and AAPA teaches
or suggests the limitation “a management module . . . operable to generate a
throttle signal that throttles operation of the processor in response to
receiving an alarm; wherein throttling operation of the processor reduces
throughput of the system resource” as recited in independent claim 1.
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We also agree with the Examiner’s determination that Shaffer’s
failure alarm in response to overheating meets the claim limitation of “an
alarm operable to indicate a failure….” (Ans. 17). In addition, we find that,
the breadth of the claim language does not preclude overheating as a failure
mechanism. Thus, Appellants’ arguments are not commensurate with the
scope of claim 1.
We further agree with the Examiner with regard to Shaffer’s teaching
of a throttle signal generated in response to receiving an alarm, as discussed
above with respect to the rejection of claim 9 (e.g., see Ans. 16-17).
Thus, we find that Appellants have not convinced us of any error in
the Examiner’s characterization of the cited art or in the Examiner’s claim
construction. Accordingly, we sustain the Examiner’s rejection of claims 1-
8, 12, 13, and 16-21.
CONCLUSIONS
(1) Appellants have not established that the Examiner erred with
respect to the unpatentability rejection of claims 1-8, 12, 13, and 16-21
under 35 U.S.C. § 103(a), and the rejection is sustained.
(2) Appellants have not established that the Examiner erred with
respect to the anticipation rejection of claims 9-11, 14, and 15 under 35
U.S.C. § 102(b), and the rejection is sustained.
(3) We find that claims 1-21 are unpatentable.
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DECISION
The decision of the Examiner to reject claims 1-21 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED

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