Ex Parte Brown et al

Patent Trial and Appeal Board

Oct 31, 2012

11348969 (P.T.A.B. Oct. 31, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/348,969 02/07/2006 Jeffrey Douglas Brown ROC920050453US1 7831
7590 10/31/2012
IBM Corporation
Intellectual Property Law Dept. 917
3605 Hwy. 52 North
Rochester, MN 55901
EXAMINER
THAMMAVONG, PRASITH
ART UNIT PAPER NUMBER
2187
MAIL DATE DELIVERY MODE
10/31/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte JEFFREY DOUGLAS BROWN, SCOTT DOUGLAS CLARK,
MARK S. FREDRICKSON, CHARLES RAY JOHNS, and
DAVID JOHN KROLAK
____________

Appeal 2010-004991
Application 11/348,969
Technology Center 2100
____________

Before SCOTT R. BOALICK, ERIC B. CHEN, and
BARBARA A. BENOIT, Administrative Patent Judges.

BENOIT, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134 involving claims to
processing commands in a computer system. The Examiner has rejected all
of the pending claims as failing to comply with the written description
requirement and also as anticipated. We have jurisdiction under 35 U.S.C.
§ 6(b). We affirm.

Appeal 2010-004991
Application 11/348,969

2
STATEMENT OF THE CASE
Appellants’ invention relates to reducing command processing latency
while maintaining memory coherence in computer systems. See generally
Abstract; Spec. 1:5-7. Claims 23-44 are on appeal, and claims 1-22 have
been cancelled. App. Br. 2. Claim 23 is illustrative and reads as follows,
with key disputed limitations emphasized:
23. A method of processing commands, comprising:
providing a system comprising a plurality of chips;
providing a memory map including memory addresses available to the
system; and
arranging the memory addresses into a plurality of groups so that:
a first of the plurality of groups corresponds to a subset of
memory addresses associated with a first chip in the system; and
if a coherent command from a bus unit in the first chip requires
access to a memory address in the first group, the coherent command
is treated as non-coherent.
The Rejections
1. The Examiner rejected claims 23-44 under 35 U.S.C. § 112, first
paragraph, as failing to comply with the written description requirement.
Ans. 3.
2. The Examiner rejected claims 23-44 under 35 U.S.C. §§ 102 (a)
and (e) as anticipated by Miller (US 2005/0114559 A1; May 26, 2005).
Ans. 4-14.

THE WRITTEN DESCRIPTION REJECTION
The Examiner finds that the originally-filed disclosure does not
describe the feature “if a coherent command from a bus unit in the first chip
requires access to a memory address in the first group, the coherent
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Application 11/348,969

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command is treated as non-coherent,” which is required by each independent
claim 23, 29, 36, and 38. Ans. 3. Appellants argue that the Examiner failed
to establish a prima facie case because the Examiner did not provide a
reasonable basis as to why the disclosure fails to reasonably convey to a
skilled artisan that Appellants possessed the claimed invention. App.
Br. 6-8.
Issue
The issue with respect to this rejection is: Under § 112, has the
Examiner erred in rejecting claims 23-44 by finding that the originally-filed
disclosure did not reasonably convey to skilled artisans that Appellants
possessed, when the application was filed, the claimed invention, including
“if a coherent command from a bus unit in the first chip requires access to a
memory address in the first group, the coherent command is treated as non-
coherent”?
Analysis
Based on the record before us, we find no error in the Examiner’s
written description rejection of illustrative claim 23. Contrary to Appellants’
argument that the Examiner’s “conclusory statements” are insufficient
according to the Manual of Patent Examination Procedure (MPEP) (App. Br.
6), we find that the Examiner has set forth a prima facie basis, which
requires a sufficient explanation to the applicant what is missing from the
written description. See Hyatt v. Dudas, 492 F.3d 1365, 1370 (Fed. Cir.
2007). As explained by the MPEP, all that may be required, when a claim is
presented by amendment (as is the case here), to meet the Examiner’s
burden of establishing a prima facie case is:
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A simple statement such as “Applicant has not pointed out
where the new (or amended) claim is supported, nor does there
appear to be a written description of the claim limitation ‘____’
in the application as filed.” may be sufficient where the claim is
a new or amended claim, the support for the limitation is not
apparent, and applicant has not pointed out where the limitation
is supported.
MPEP § 2163.04 (I)(B) (8th Ed. 2001) (Rev. 9, Aug. 2012); accord Hyatt v.
Dudas, 492 F.3d at 1370 (holding that “[MPEP] § 2163.04(I)(B) as written
is a lawful formulation of the prima facie standard for a lack of written
description rejection.”).
Here, the Examiner identified the claim limitation at issue and
indicated that (i) the claim including the limitation was added by
amendment, (ii) Appellants did not indicate support for the newly presented
claim, and (iii) it was unclear to the Examiner where this claim limitation
was taught by the Specification. Ans. 3, 17. As such, the Examiner
followed the procedure suggested by the MPEP to establish a prima facie
case. Moreover, the Examiner further indicated a portion of Appellants’
Specification that discussed non-coherent commands and explained the
Examiner’s conclusion that the indicated portion of the Specification did not
provide explicit or implicit support for the limitation at issue. Ans. 3 (citing
Spec. 26, l. 20 to 27, l. 10). Appellants were notified of what the Examiner
found missing by way of written description support. Accordingly, we
conclude that this is sufficient in these circumstances to meet the Examiner’s
burden to set forth a prima facie basis.
Appellants point to page 1, lines 21-28 and page 4, lines 20-27 of their
Specification as providing support for the limitation at issue: “if a coherent
command from a bus unit in the first chip requires access to a memory
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address in the first group, the coherent command is treated as non-coherent.”
The test for determining compliance with the written description
requirement is “whether the disclosure of the application relied upon
‘reasonably conveys to the artisan that the inventor had possession at that
time of the . . . claimed subject matter.’” Vas-Cath, Inc. v. Mahurkar, 935
F.2d 1555, 1563 (Fed. Cir. 1991).
Appellants do not persuasively demonstrate error in the Examiner’s
prima facie case. The portions of the Specification relied on by Appellants
describe maintaining coherence in a conventional system (Spec. 1, ll. 21-28)
and the invention’s use of a system map which does not require system-wide
memory coherency and may only require maintaining coherence of
addresses included in the same group or domain of addresses (Spec. . 4, ll.
20-27). Notably, however, these portions of the Specification do not teach,
expressly or inherently, the concept of treating a coherent command as a
non-coherent command, as required by claim 23.
Accordingly, we are not persuaded of Examiner error in the
Examiner’s rejection of claim 23 or its dependent claims 24-28. Therefore,
we will sustain the written description rejection of claims 23-28.
Each independent claim 23, 29, 36, and 38 recites the limitation “if a
coherent command from a bus unit in the first chip requires access to a
memory address in the first group, the coherent command is treated as non-
coherent.” Therefore, for the same reasons discussed above with respect to
claim 23, we are not persuaded that the Examiner erred in rejecting
independent claims 29, 36, and 38 or their respective dependent claims 30-
35, 37, and 39-44. Accordingly, we will sustain the written description
rejection of claims 29-44.
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ANTICIPATION REJECTION
The Examiner found that Miller disclosed every recited limitation of
illustrative claim 23. Ans. 4-5. Appellants argue, among other things, that
Miller does not disclose treating a coherent command as non-coherent, as
recited by claim 23. App. Br. 10-14.
Issue
The issue with respect to this rejection is: Under § 102, has the
Examiner erred in rejecting claims 23-44 by finding that Miller discloses “if
a coherent command from a bus unit in the first chip requires access to a
memory address in the first group, the coherent command is treated as non-
coherent”?
Analysis
Under the standards required by § 102, we are unable to affirm the
Examiner’s anticipation rejections.
1
The Examiner found that Miller
discloses treating a coherent command as non-coherent in paragraph 0005
where Miller discloses that “all DMA requests must adhere to coherency
rules to maintain cache coherency” and paragraph 0030 where Miller
discloses “a DMA request would be forwarded to the memory controller in a
non-coherent or coherent manner based on the memory address range.”
Ans. 5. Appellants agree with the Examiner that Miller discloses, in
paragraph 0030, that the DMA request may be forwarded in a coherent or
non-coherent manner. App. Br. 13. Appellants, however, disagree with the
Examiner’s finding that the limitation “if a coherent command from a bus
unit in the first chip requires access to a memory address in the first group,

1
Our analysis will treat the Examiner’s rejections under §§ 102 (a) and (e)
together because our analysis is the same for both rejections.
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the coherent command is treated as non-coherent” is met because paragraphs
0005 and 0030 teach that “a DMA request, which adheres to coherency
rules, can [be] forwarded in a coherent or non-coherent manner based on its
memory address range.” Ans. 21.
We agree with Appellants. Under § 102, the Miller disclosure falls
short. Claim 23 requires that a coherent command is treated as non-
coherent, which is not disclosed, expressly or inherently, in the cited
portions of Miller. Under § 102, Miller’s disclosure that a DMA request can
be forwarded in a coherent or a non-coherent manner based on its memory
address range is not sufficient to anticipate the limitation “if a coherent
command from a bus unit in the first chip requires access to a memory
address in the first group, the coherent command is treated as non-coherent.”
Accordingly, we are unable to affirm the Examiner’s anticipation
rejections of claim 23 or its dependent claims 24-28.
Each independent claim 23, 29, 36, and 38 recites the limitation if a
coherent command from a bus unit in the first chip requires access to a
memory address in the first group, the coherent command is treated as non-
coherent. Therefore, for the same reasons discussed above with respect to
claim 23, we are unable to affirm the anticipation rejections of independent
claims 29, 36, and 38 or their respective dependent claims 30-35, 37, and 39-
44.

CONCLUSION
Under § 112, first paragraph the Examiner did not err in rejecting
claims 23-44. Under § 102, the Examiner erred in rejecting claims 23-44.

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Application 11/348,969

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DECISION
The Examiner’s decision rejecting claims 23-44 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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