Ex Parte Bose et al

Patent Trial and Appeal Board

Oct 29, 2018

13211701 (P.T.A.B. Oct. 29, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/211,701 08/17/2011
48915 7590 10/31/2018
CANTOR COLBURN LLP-IBM YORKTOWN
20 Church Street
22nd Floor
Hartford, CT 06103
FIRST NAMED INVENTOR
Pradip Bose
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
YOR920110512US1 4756
EXAMINER
VICARY, KEITH E
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
10/31/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
usptopatentmail@cantorcolbum.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PRADIP BOSE, ALPER BUYUKTOSUNOGLU,
JEFFREY HASKELL DERBY,
MICHELE MARTINO FRANCESCHINI,
ROBERT KEVIN MONTOYE, and AUGUSTO J. VEGA
Appeal2018-001916
Application 13/211,701 1
Technology Center 2100
Before ALLEN R. MacDONALD, JOSEPH P. LENTIVECH, and
MICHAEL J. ENGLE, Administrative Patent Judges.
ENGLE, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1, 3-9, 11-16, and 22, which are all of the claims pending in the
application. We have jurisdiction under 35 U.S.C. § 6(b ).
We AFFIRM.
Technology
The application relates to "local computation logic embedded in a
register file [ of a central processing unit] to accelerate programs." Spec.
Title ( capitalization omitted).
1 According to Appellants, the real party in interest is International Business
Machines Corp. App. Br. 3.
Appeal 2018-001916
Application 13/211, 701
Illustrative Claim
Claim 1 is illustrative and reproduced below with certain limitations at
issue emphasized:
1. A central processing unit embodied as hardware, comprising:
a hardware pipeline configured to receive instructions,
said hardware pipeline comprising a resource configured to
execute at least some of said instructions;
a register file located outside the hardware pipeline and
internal to the central processing unit, said register file
comprising a plurality of subarrays; and
at least one computation element embedded within the
register file, said at least one computation element directly
connected to at least one subarray of said plurality of subarrays;
wherein said hardware pipeline is configured to execute at
least some of said instructions according to a first mode that
comprises using said resource to execute said at least some of
said instructions;
wherein said hardware pipeline is further configured to
execute at least some of said instructions according to a second
mode that comprises said hardware pipeline:
accessing said at least one computation element
through a direct connection that does not rely on a direct
memory access unit; and
using said at least one computation element to
execute at least some of said instructions.
Rejections
Claims 1, 3-9, 11-16, and 22 stand rejected under 35 U.S.C. § 112,
first paragraph as failing to comply with the written description requirement.
Final Act. 5.
Claims 1, 3-9, 11-16, and 22 stand rejected under 35 U.S.C. § 112,
second paragraph as indefinite. Final Act. 7.
2
Appeal 2018-001916
Application 13/211, 701
Claims 1, 3-9, 11-15, and 22 stand rejected under 35 U.S.C. § I03(a)
as obvious over the combination of Shen et al., Modern Processor Design:
Fundamentals of Superscalar Processors (2005) and Chi (US 2012/0124248
Al; May 17, 2012). Final Act. 11.
Claim 16 stands rejected under 35 U.S.C. § I03(a) as obvious over the
combination of Shen, Chi, and Lindner et al. (US 2003/0088757 Al; May 8,
2003). Final Act. 21.
ISSUE
Did the Examiner err in finding the combination of Shen and Chi
teaches or suggests "at least one computation element embedded within the
register file," as recited in claim 1?
ANALYSIS
§ 103
Claim 1 recites "[a] central processing unit ... comprising: ... a
register file located ... internal to the central processing unit" and "at least
one computation element embedded within the register file." Independent
claim 22 recites commensurate limitations.
The Examiner finds that "Shen discloses ... a register file internal to
a central processing unit" and "Chi discloses ... a computation element
embedded within a storage." Ans. 4.
Appellants argue that Chi teaches a main memory (e.g., RAM)
"external to a microprocessor" can include computational elements, but "the
Examiner points to no references or 'known methods' by which a register
file can have a computational element located within [ the CPU]." Reply Br.
2-3 ( emphasis added).
3
Appeal 2018-001916
Application 13/211, 701
We agree with the Examiner that a "register file" is a form of storage
and more specifically a form of memory. Ans. 11; Shen 112 ("Finally, the
fastest, smallest, and most expensive element in a modem memory hierarchy
is the register file.") ( emphasis added); Chi ,r 21. We also agree with the
Examiner that Chi "does not criticize, discredit, or otherwise discourage the
embedding of a computation element within a register file" and therefore
"does not teach away from the present invention." Ans. 12. Nevertheless,
"not teaching away" is not the same as "teaching." Here, we agree with
Appellants that the Examiner has not shown anything in Shen or Chi that
teaches or suggests embedding a computation element in a register file
within a CPU rather than main memory outside a CPU. On the record
before us, it is not clear that a computation element embedded within a
register file would be a "combination of familiar elements according to
known methods" that "does no more than yield predictable results." KSR
Int'! Co. v. Teleflex Inc., 550 U.S. 398,416 (2007).
Accordingly, we do not sustain the Examiner's rejection of
independent claims 1 and 22, and their dependent claims 3-9 and 11-16.
§ 112, first and second paragraphs
The Examiner rejected all pending claims under§ 112, first and
second paragraphs. Final Act. 5, 7. Appellants submitted amendments that
they argue "alleviate the section 112 rejections," but acknowledge those
amendments "were not entered." Reply Br. 2; App. Br. 5. Appellants do not
otherwise address the § 112 rejections in the Appeal Brief.
Based on the claims and rejections currently before us, we sustain the
Examiner's rejections of claims 1, 3-9, 11-16, and 22 under§ 112, first and
second paragraphs.
4
Appeal 2018-001916
Application 13/211, 701
DECISION
For the reasons above, we affirm the Examiner's decision rejecting
claims 1, 3-9, 11-16, and 22 under§ 112, first and second paragraphs, but
we reverse the Examiner's decision rejecting those claims under§ 103.
Because we affirm at least one rejection for every appealed claim, we
designate this Decision as an affirmance.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(±).
AFFIRMED
5