Ex Parte Bohrer et al

Board of Patent Appeals and Interferences

Jan 30, 2012

10948407 (B.P.A.I. Jan. 30, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/948,407 09/23/2004 Patrick Joseph Bohrer AUS920040286US1 9670
61043 7590 01/30/2012
IBM CORPORATION (MH)
c/o MITCH HARRIS, ATTORNEY AT LAW, L.L.C.
P.O. BOX 7998
ATHENS, GA 30604
EXAMINER
MAMO, ELIAS
ART UNIT PAPER NUMBER
2184
MAIL DATE DELIVERY MODE
01/30/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte PATRICK JOSEPH BOHRER, AHMED GHEITH,
PETER HEINER HOCHSCHILD, RAMAKRISHNAN RAJAMONY,
HAZIM SHAFI, and BALARAM SINHAROY
____________

Appeal 2009-013545
Application 10/948,407
Technology Center 2100
____________

Before ALLEN R. MacDONALD, DENISE M. POTHIER,
and BRUCE R. WINSOR, Administrative Patent Judges.

WINSOR, Administrative Patent Judge.

DECISION ON APPEAL

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Application 10/948,407

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Appellants appeal under 35 U.S.C. § 134(a) from a Non-Final
Rejection of claims 1-30, which constitute all the claims pending in this
application. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.

STATEMENT OF THE CASE
Appellants’ “invention relates generally to processors and computing
systems, and more particularly, to a cache injection mechanism to accelerate
input/output (I/O) operations in multiprocessor systems.” Spec 1:12-15.
Claim 1, which is illustrative of the invention, reads as follows:
1. A method for performing a direct memory access (DMA)
transfer within a processing system including multiple
processors, said method comprising:
initiating said DMA transfer to a DMA transfer target
memory image within a DMA transfer target memory over a
bus;
determining in a cache controller managing a cache
memory associated with a particular one of said multiple
processors that said DMA transfer is occurring on said bus;
responsive to determining that said DMA transfer is
occurring, copying data being transferred in said DMA transfer
to a cache line in said cache memory during said DMA transfer;
and
targeting said particular processor for executing a routine
that accesses memory addresses of said DMA transfer target
memory image, whereby said particular processor processes
data transferred by said DMA transfer.
The Examiner relies on the following prior art in rejecting the claims:
Woods US 5,428,799 June 27, 1995
Borrill US 5,588,131 Dec. 24, 1996
Funk US 5,784,697 July 21, 1998
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Wei US 2005/0033948 Al Feb. 10, 2005
McDonald US 7,159,216 B2 Jan. 2, 2007
Claims 1-3, 5, 7, 9-13, 15, 17, 19-24, 26, and 28 stand rejected under
35 U.S.C. § 103(a) as obvious over Borrill and Funk (Ans. 3-11, 13-14).
Claims 4, 6, 14, 16, 25, and 27 stand rejected under 35 U.S.C.
§ 103(a) as obvious over Borrill, Funk, and McDonald (Ans. 11-12, 13-14).
Claims 8, 18, and 29 stand rejected under 35 U.S.C. § 103(a) as
obvious over Borrill, Funk, and Woods (Ans. 12-13, 14).
Claim 30 stands rejected under 35 U.S.C. § 103(a) as obvious over
Borrill and Wei (Ans. 14-16).
Rather than repeat the arguments here, we make reference to the Brief
and the Answer for the respective positions of Appellants and the Examiner.
Only those arguments actually made by Appellants have been considered in
this decision. Arguments that Appellants did not make in the Brief have not
been considered and are deemed to be waived. See 37 C.F.R.
§ 41.37(c)(1)(vii) (2010).

ISSUES
The pivotal issues presented by Appellants’ contentions are as
follows:
Did the Examiner err in rejecting claim 1 under 35 U.S.C. § 103(a) as
obvious over Borrill and Funk? More particularly, does Funk when
combined with Borrill, teach or suggest “targeting [a] particular processor
for executing a routine that accesses memory addresses of [a] DMA transfer
target memory image, whereby said particular processor processes data
transferred by said DMA transfer,” as recited in claim 1?
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Did the Examiner err in rejecting claim 2 under 35 U.S.C. § 103(a) as
obvious over Borrill and Funk? More particularly, does Funk, when
combined with Borrill, teach or suggest that “said targeting comprises
identifying said particular processor subsequent to completion of said DMA
transfer,” as recited in claim 2?
Did the Examiner err in rejecting claim 30 under 35 U.S.C. §103(a) as
obvious over Borrill and Wei? More particularly, does the combination of
Borrill and Wei teach or suggest “executing an interrupt routine on one of
the multiple processors other than the particular processor to handle the
interrupt,” as recited in claim 30?

ANALYSIS
Claim 1
The Examiner relies on Funk as disclosing “a method for assigning a
process/ a task using a process nodal affinity in a NUMA multiprocessor
system for enhanced performance (col. 2, lines 1-20 and col. 7, lines 38-
50).” (Ans. 4.) Appellants assert that:
neither Funk nor the combined teachings of Borrill and Funk
provide any guidance as to selection of a particular processor
within a node, and therefore do not make obvious the targeting
of a particular processo [sic] for executing the selected routine
that uses the specific memory addresses of the DMA transfer
target memory image. In fact, because processes in Funk are
assigned to nodes, any processor within a node (e.g., any of
processors P1- PN in Figure 1 of Funk), would be "fair game"
for executing any routine processing data contained in node 110
in Figure 1 of Funk.
Further, the teachings of Funk center around assigning
and linking processes to nodes based on the locality of main
memory used by the process, in order to localize accesses by
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the nodes in the NUMA architecture employed in Funk. In
general, such memory-level localization would be irrelevant to
the processing of DMA transfer data snarfed by a cache
associated with a particular processor, as the cached data would
already be at the particular processor (i.e., accesses to the DMA
transfer data would "hit" in the cache).
(Br. 10). The Examiner responds that “even though Funk's process
assignment mechanism is designed to assign processes at a node level, using
this known efficiency/performance improvement technique in the same way
to a cache memory level of a processing system with direct memory access
(DMA) would have resulted [in] the claimed invention.” (Ans. 19.)
The test for obviousness is not whether the features of a
secondary reference may be bodily incorporated into the
structure of the primary reference; nor is it that the claimed
invention must be expressly suggested in any one or all of the
references. Rather, the test is what the combined teachings of
the references would have suggested to those of ordinary skill
in the art.
In re Keller, 642 F.2d 413, 425 (CCPA 1981) (citations omitted).
We agree with the Examiner.
[I]f a technique has been used to improve one device, and a
person of ordinary skill in the art would recognize that it would
improve similar devices in the same way, using the technique is
obvious unless its actual application is beyond his or her skill.”
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007). As the Examiner
has explained (Ans. 19), a person of ordinary skill in the art would have
recognized that Funk’s process assignment technique (see generally Funk
Abstract) would improve Borrill’s technique for caching data during a DMA
transfer (see Borrill col, 2, ll. 63-67) by assigning processors for subsequent
processing of the transferred data in the same way as Funk assigns nodes for
processing of data.
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Based on the evidence of record, Appellants have not persuaded us of
error in the Examiner’s findings and explanations. Accordingly, we will
sustain the rejection of: (1) claim 1; (2) claims 11 and 23, which were argued
together with claim 1 (Br. 9); and (3) dependent claims 4-10, 12, 15-22, and
26-29, which were not separately argued (Br. 9-10, 12).
Claim 2
Appellants contend that “Borrill and Funk do not disclose or suggest
identifying a particular processor subsequent to completion of the DMA
transfer.” (Br. 11.) The Examiner responds that “[i]dentifying the particular
processor either before or after the completion of DMA data transfer is
merely an alternate arrangement or a design choice which falls with in [sic]
the level of ordinary skill in the art.” (Ans. 20.) However, “rejections on
obviousness grounds cannot be sustained by mere conclusory statements;
instead, there must be some articulated reasoning with some rational
underpinning to support the legal conclusion of obviousness.” In re Kahn,
441 F.3d 977, 988 (Fed. Cir. 2006). We find that Examiner’s explanation is
just such a conclusory statement, unsupported by rational underpinning, such
as evidence from the record, and we therefore conclude that the Examiner
has not established a prima facie case of obviousness for claim 2.
Accordingly, we will not sustain the rejection of claim 2, of claims 13
and 24, which include a substantially similar limitation, or of claims 3, 14,
and 25, which depend from claims 2, 13, and 24 respectively.
Claim 30
The Examiner found that Borrill discloses:
-receiving an interrupt indicating completion of the DMA
transfer (Note: it is inherent to generate interrupt after
completion of DMA transfer);
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-executing an interrupt routine on one of the multiple
processors other than the particular processor to handle the
interrupt and schedule a deferred procedure call targeting said
particular processor for execution; and executing the deferred
procedure call on the particular processor to access memory
addresses of the DMA transfer target memory image, whereby
the particular processor processes data transferred by said DMA
transfer (Note: Borrill '131 inherently teach a deferred
procedure call since it is a mechanism that allow a processor
while executing a critical task to perform less critical execution
by deferring their execution to some later time).
(Ans. 15-16.) The Examiner further explains:
The Appellant argued that the steps of executing an
interrupt routine in one of a processor and executing a deferred
procedure call by a selected processor are not taught by the
references[;] however, these steps are the necessary steps that
are created when the teachings of Borrill and Wei are combined
and implemented by the person of ordinary skill in the art in
order to make the improvement or the modification practical or
operational.
(Ans. 24-25).
Appellants’ contend that:
in Claim 30, the targeted execution in response to an interrupt
indicating completion of the DMA transferred occurs in two
parts: 1) executing an interrupt routine on one of the processors
other than the particular processor and 2) executing a deferred
procedure call scheduled by the interrupt routine on the
particular processor. Neither Borrill nor Wei disclose such
processing, nor does their combination, with or without the
teachings of Funk as noted above, suggest the specific interrupt
technique recited in Claim 30.
(Br. 13-14.)
We have reviewed the Examiner’s findings and explanations, and do
not find any reference to a passage in Borrill, Wei, or Funk that discloses
that the interrupt routine is executed on a different one (i.e., “other than the
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particular processor”) of the processors from the particular processor that
executes the deferred procedure calls. Although the Examiner makes
findings that interrupts and deferred procedure calls are inherently disclosed
by Borrill, the Examiner makes no finding that using different processors for
the interrupt routine and the deferred procedure call (i.e., one of the multiple
processors other than the particular processor and the particular processor
respectively) is explicitly or inherently disclosed by Borrill.
We find that the Examiner erred in rejecting claim 30 because the
Examiner’s findings and explanations (Ans. 15-16, 24-25) fail to address
limitations recited in the claim. Accordingly, we will not sustain the
rejection of claim 30

DECISION
The decision of the Examiner to reject claims 1, 4-12, 15-23, and
26-29 is affirmed.
The decision of the Examiner to reject claims 2, 3, 13, 14, 24, 25, and
30 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2010).

AFFRMED-IN-PART

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