Ex Parte Bockhaus

Patent Trial and Appeal Board

Mar 20, 2015

11048830 (P.T.A.B. Mar. 20, 2015)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte JOHN WILLIAM BOCKHAUS
____________

Appeal 2012-012358
Application 11/048,830
Technology Center 2100
____________

Before JOHN A. JEFFERY, MARC S. HOFF, and DENISE M. POTHIER,
Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision to reject claims 1, 4–6, 9, 11–17, 19–22, 25–30, and 33–43. We
have jurisdiction under 35 U.S.C. § 6(b). We affirm.

STATEMENT OF THE CASE
Appellant’s invention uses memory in a computer system by (1)
storing a received direct memory access (DMA) transaction in a request
address first-in, first-out buffer (“RAF”), and (2) issuing at least one prefetch
memory request if the transaction is read request. The process is repeated
for following entries in the RAF. See generally Abstract; Spec. ¶¶ 12–16.
Claims 1 and 9 are illustrative:
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1. A memory utilization method in a computer system, the
method comprising:
storing DMA transactions received from an entity in a request
address first-in, first-out buffer (“RAF”);
processing the DMA transactions stored in the RAF according to
the order in the RAF via a read request process and a write request
process;
process the DMA transactions stored in the RAF via a preread
process comprising:
skipping write request in the DMA transactions stored in the RAF;
locating a first DMA transaction stored in the RAF that is a read
request;
responsive to locating the read request, issuing at least one prefetch
memory request in connection with the read request; and
locating a next DMA transaction stored in the RAF that is a read
request wherein the locating a next DMA transaction that is a read
request and the issuing at least one prefetch memory request are
repeated until all read requests in the DMA transactions stored in the
RAF have been processed.

9. A memory utilization method in a computer system, the
method comprising;

responsive to receipt of a DMA transaction from an entity,
storing the DMA transaction in a request address first-in first out
buffer (“RAF”), wherein DMA transactions are stored in the RAF in
an order in which they are received;

processing the DMA transactions stored in the RAF according
to the order in which they were received via a read request process
and a write request process;

processing the DMA transactions stored in the RAF via a
preread process comprising:

initializing a pointer to point to an entry of the RAF;

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determining whether a DMA transaction stored in the entry of
the RAF to which the pointer points in a DMA read request;

responsive to a determination that the DMA transaction stored
in an entry of the RAF to which the pointer points is a DMA read
request, issuing at least one prefetch memory request in connection
witht the DMA read request and otherwise forgoing issuance of at
least one prefetch memory request in connection with the DMA
transaction stored in eh entry of the RAF to which the pointer points;
and

responsive to completion of the issuing or forgoing, advancing
the pointer to point to a next entry of the RAF, wherein the
determining, issuing or forgoing, and advancing are repeated until all
of the DMA transactions stored in the RAF have been processed.

THE REJECTIONS
The Examiner rejected claims 9, 11–16, and 36 under 35 U.S.C.
§ 102(b) as anticipated by Miller (US 5,915,104; June 22, 1999). Ans.
13–16.
1

The Examiner rejected claims 1, 4–6, 17,
2
19–22, 25–30, 33–35, and
37–43 under 35 U.S.C. § 103(a) as unpatentable over Miller and Khare (US
7,124,252 B1; Oct. 17, 2006). Ans. 4–13.

1
Throughout this opinion, we refer to the Appeal Brief filed January 5, 2012
(“Br.”) and the Examiner’s Answer mailed June 8, 2012 (“Ans.”).
2
Although the Examiner omits claim 17 from the statement of the rejection,
the Examiner nonetheless includes that claim in the corresponding
discussion. Compare Ans. 4 with Ans. 13. Accordingly, we present the
correct claim listing here for clarity, and deem the Examiner’s error
harmless.
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THE ANTICIPATION REJECTION
The Examiner finds that Miller discloses every recited element of
independent claim 9 including processing DMA transactions stored in the
RAF (1) according to the order in which they were received via read request
and write request processes, and (2) via a preread process, the latter of which
is said to correspond to Miller’s prefetching process in connection with read
operations. Ans. 14–21. According to the Examiner, the recited pointer-
based limitations are inherent to processing entries sequentially in Miller’s
first-in-first-out (FIFO) queue that can hold up to fifteen read requests. Ans.
15–16, 19–21.
Appellant argues that Miller does not teach or suggest the three
recited processes, namely a (1) read request process; (2) write request
process; and (3) preread process, but rather performs read and write
operations. Br. 11. According to Appellant, Miller’s read operation is not a
preread process, but rather is a normal read operation that includes the
possibility of prefetching. Br. 12. Appellant adds that Miller does not teach
or suggest a pointer, let alone (1) initialize a pointer to point to an RAF
entry, or (2) teach the other recited limitations that refer to a pointer. Br.
12–13.

ISSUE
Under § 102, has the Examiner erred in rejecting claim 9 by finding
that Miller processes DMA transactions stored in a RAF via the three recited
processes including a preread process, where the preread process (1)
initializes a pointer to point to an entry of an RAF; (2) issues at least one
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prefetch memory request responsive to determining that the pointed-to DMA
transaction is a DMA read request, and otherwise forgoes issuing that
request; (3) advances the pointer to point to a next entry responsive to
completing the previous step; and (4) repeats steps (2) and (3) until all stored
DMA transactions have been processed?

ANALYSIS
We sustain the Examiner’s rejection of claim 9 essentially for the
reasons indicated by the Examiner. Ans. 14–21. First, we see no error in the
Examiner’s finding that Miller processes DMA transactions stored in a RAF
via the three recited processes, namely via distinct write, read, and preread
processes. Ans. 17–19 (distinguishing these processes in Miller).
Appellant’s contention that Miller’s read operation is not a preread process,
but rather is a normal read operation that “includes the possibility of
prefetching” (Br. 12) is unavailing and not commensurate with the scope of
the claim. Although prefetching is part of Miller’s read operation in Figure
3, it is nonetheless a distinct process that is executed only if a prefetch
attribute is set in step 305; otherwise, buffers are read in step 310. See
Miller, col. 6, ll. 48–66. Therefore, Miller’s read operation in Figure 3 has
at least two distinct processes, namely (1) a “read request process” that
excludes steps 306 to 309, and (2) a “preread process” that includes those
steps. Given these two distinct processes in Figure 3, and the relied-upon
write request process in Figure 4, the Examiner’s position that Miller teaches
the three recited DMA transaction processes is reasonable.
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Nor do we find error in the Examiner’s reliance on Miller’s request
FIFO
3
buffer for teaching initializing a pointer to point to an entry in that
buffer, and issuing a prefetch memory request responsive to determining that
the pointed-to transaction is a DMA read request. As the Examiner explains,
nothing in the claim precludes queuing and accessing entries sequentially in
Miller’s request FIFO that would inherently point to entries to effect this
sequential process. See Ans. 15–16, 19–21. Even if Miller’s request FIFO
provides the next item in line to the request dispatcher as Appellant contends
(Br. 12–13), nothing in the claim precludes the sequential, pointer-based
functionality inherent to this FIFO-based process and associated issuance of
prefetch memory requests for read request determinations as the Examiner
indicates. See Ans. 14–21.
Therefore, we are not persuaded that the Examiner erred in rejecting
claim 9, and claims 11–16 and 36 not argued separately with particularity.

THE OBVIOUSNESS REJECTION
The Examiner finds that Miller discloses every recited element of
claim 1 except for the preread process skipping write requests in stored
DMA transactions. Ans. 4–6. The Examiner reasons that because Khare’s
process in Figure 3 executes steps 315 and 325 for read requests, this
functionality “depart[s] from” write requests and their associated functions
by not executing step 335. Ans. 6–7, 21–23. Alternatively, the Examiner
finds that Khare discloses every recited element of claim 1 except for DMA

3
Although Miller labels this buffer as a “request fifo” in column 5, lines 57
and 61, we nonetheless capitalize this abbreviation for consistency with
standard nomenclature in the art. See, e.g., Microsoft Computer Dictionary
211 (5th ed. 2002). Accord Br. 12 (adopting this convention).
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transactions, but cites Miller for teaching this feature. Ans. 7–8. In light of
these alternative positions, the Examiner concludes that claim 1 would have
been obvious over the cited references’ collective teachings. Ans. 4–9, 21–
23.
Appellant reiterates similar arguments regarding Miller’s alleged
shortcomings regarding the three recited processes and recited preread
process functionality. Br. 13–14. Appellant adds that Khare does not
process stored DMA transactions via a preread process, let alone a preread
process that skips write requests in those transactions as claimed. Br. 15.
The Examiner’s alternative interpretation of the cited references is also said
to be deficient for similar reasons. Br. 15. Appellant further argues other
recited limitations summarized below.

ISSUES
Under § 103, has the Examiner erred by finding that Miller and Khare
collectively would have taught or suggested:
(1) processing DMA transactions stored in a RAF via the three recited
processes including a preread process, where the preread process skips write
requests in the transactions as recited in claim 1?
(2) the preread register and pointer control logic recited in claim 25?

ANALYSIS
Claims 1, 4–6, 17, 19–22, 30, 33–35, 37–39, 42, and 43
We sustain the obviousness Examiner’s rejection of claim 1
essentially for the reasons indicated by the Examiner for either alternative
interpretation. Ans. 4–7, 21–23. First, Appellant’s arguments regarding
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Miller’s alleged shortcomings regarding the three recited processes,
including the recited preread process (Br. 13–14), are unavailing for the
reasons noted previously. Appellant’s arguments regarding Miller not
teaching or suggesting skipping write requests in stored DMA transactions
as claimed (Br. 14) are likewise unavailing, for the Examiner cites Khare—
not Miller—for this feature in connection with both alternative
interpretations. See Ans. 6–8, 21–23.
Appellant’s arguments regarding Khare’s lacking a preread process
that skips write requests (Br. 15) are likewise unpersuasive. As the
Examiner indicates, nothing in the claim precludes the functionality of
Khare’s Figure 3 that, by executing steps 315 and 325 for read requests,
effectively departs from—and thus, skips—write requests and their
associated functions by not executing step 335. See Ans. 6–7, 21–23. This
functionality not only at least suggests a preread process, but also skipping
write requests under certain conditions.
Therefore, we are not persuaded that the Examiner erred in rejecting
claim 1, and claims 4–6, 17, 19–22, 30, 33–35, 37–9, 42, and 43 not argued
separately with particularity.

Claims 25–29, 40, and 41
We also sustain the Examiner’s rejection of claim 25 reciting, in
pertinent part, (1) a preread register associated with an entity for tracking the
DMA transaction currently being processed in the preread process, and (2)
pointer control logic configured to control a preread pointer as claimed. The
Examiner finds that these limitations are not only taught or suggested by
Miller, but also by Khare. Compare Ans. 10–11 (mapping the recited
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preread register and pointer control logic limitations to various passages in
Miller) with Ans. 11–12 (mapping same limitations to Khare’s disclosure).
Accord Ans. 25–26 (reiterating this latter mapping).
Therefore, Appellant’s arguments regarding Miller’s alleged
shortcomings in connection with the recited preread register and pointer
control logic (Br. 16) do not address—let alone persuasively rebut—the
Examiner’s alternative reliance on Khare for teaching these features. For
this reason alone, we are unpersuaded of error in the Examiner’s rejection of
claim 25. Nevertheless, we are also unpersuaded of error in the Examiner’s
alternative reliance on Miller for teaching these features for the reasons
indicated by the Examiner. Ans. 23–24.
Therefore, we are not persuaded that the Examiner erred in rejecting
claim 25, and claims 26–29, 40, and 41 not argued separately with
particularity.

CONCLUSION
The Examiner did not err in rejecting (1) claims 9, 11–16, and 36
under § 102, and (2) claims 1, 4–6, 17, 19–22, 25–30, 33–35, and 37–43
under § 103.
DECISION
The Examiner’s decision rejecting claims 1, 4–6, 9, 11–17, 19–22,
25–30, and 33–43 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED
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