Ex Parte BLAKE et al

Patent Trial and Appeal Board

Aug 6, 2018

14692959 (P.T.A.B. Aug. 6, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/692,959 04/22/2015
73459 7590 08/08/2018
NIXON & V ANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11 TH FLOOR
ARLINGTON, VA 22203
FIRST NAMED INVENTOR
Geoffrey BLAKE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
JRL-550-1865 1082
EXAMINER
HO,AAROND
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
08/08/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GEOFFREY BLAKE, ALI GHASSAN, and
MITCHELL HA YEN GA
Appeal2018-002519
Application 14/692,959 1
Technology Center 2100
Before ST. JOHN COURTENAY III, JASON J. CHUNG, and
JAMES W. DEJMEK, Administrative Patent Judges.
DEJMEK, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1 and 4--20. Appellants have canceled claims 2 and 3. See Final
Act. 2. We have jurisdiction over the remaining pending claims under
35 U.S.C. § 6(b).
We reverse.
1 Appellants identify ARM LIMITED as the real party in interest. App.
Br. 3.
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Application 14/692,959
STATEMENT OF THE CASE
Introduction
Appellants' disclosed and claimed invention is generally directed to
the control of memory systems. Spec. 1. In a disclosed embodiment, a data
processing system comprises a processor core, memory bank ( e.g., DRAM
and non-volatile memory banks), a memory controller, a translation
lookaside buffer (TLB), and a hint generator. Spec. 4---6, Fig. 1. The TLB
stores a subset of mapping data entries from a page table data, which
"describes the virtual-to-physical address mapping, and other mapping
attributes, associated with the entire memory address space." Spec. 4.
According to the Specification, the TLB may be thought of as a cache of
recently used mapping data entries. Spec. 4. "If there is insufficient storage
space within the translation lookaside buffer 6 for a newly read mapping
data entry, then a currently stored mapping data entry 10 will be evicted in
order to male space available for the new entry." Spec. 4. Additionally, a
hint generator is coupled to the TLB and memory controller and provides
hint data to the memory controller ( e.g., whether the mapping data entries
have been loaded or evicted from the mapping circuitry) such that the
memory controller may control different regions of the memory space, for
example, by powering down a bank of memory that is being infrequently
accessed. Spec. 5---6.
Claim 1 is illustrative of the subject matter on appeal and is
reproduced below with the disputed limitation emphasized in italics:
1. Apparatus for processing data comprising:
mapping circuitry to store one or more mapping data
entries respectively indicative of a mapping between a region of
virtual addresses within a virtual address space and a region of
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Application 14/692,959
physical addresses within a physical address space and to
perform a mapping from a virtual address within said region of
virtual addresses to a physical address within said region of
physical addresses;
hint generating circuitry coupled to said mapping circuitry
to generate hint data indicating mapping data entries that have
been loaded into the mapping circuitry and mapping data entries
that have been evicted from the mapping circuitry; and
storage control circuitry to control, in dependence upon
said hint data, how data corresponding to respective different
regions of physical addresses is stored within a memory system.
The Examiner's Rejections
1. Claims 1, 4--6, 9, 10, 12-16, 19, and 20 stand rejected under
35 U.S.C. § I02(a)(2) as being anticipated by Klein (US 2014/0025923 Al;
Jan. 23, 2014). Final Act. 3-11.
2. Claims 7 and 8 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Klein and Yanchao Lu et al., Rank-Aware Dynamic
Migrations and Adaptive Demotions for DRAM Power Management,
arXiv:I409.5567vl 1-19 (Cornell University Sept. 2014) ("Lu"). Final
Act. 11-13.
3. Claim 11 stands rejected under 35 U.S.C. § 103 as being
unpatentable over Klein and Elliott Cooper-Balis & Bruce Jacob, Fine-
Grained Activation for Power Reduction in DRAM, IEEE Computer Society,
34--47 (May/June 2010) ("Cooper-Balis"). Final Act. 13-15.
4. Claims 17 and 18 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Klein and Index of Lectures by Keshav Pingali,
https://www.cs.utexas.edu/-pingali/CS378/2015sp/lectures (last visited
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Sept. 26, 2016), Cache Coherence in Shared-Memory Architectures (adapted
from a lecture by Ian Watson) ("Pingali"). Final Act. 15-17.
ANALYSIS 2
Claims 1, 4-6, 9, 10, 12-16, 19, and 20
The Examiner finds Klein anticipates, inter alia, independent claim 1.
Final Act 3-5. Klein is directed to memory management in a hierarchical
memory system. Klein ,r 2. In a disclosed embodiment, Klein describe a
memory management system comprising a translation lookaside buff er and
an XLAT translation (translate translation) device. Klein ,r 21, Fig. 2.
Figure 4 of Klein is illustrative and is reproduced below:
2 Throughout this Decision, we have considered the Appeal Brief, filed
September 22, 2017 ("App. Br."); the Reply Brief, filed January 2, 2018
("Reply Br."); the Examiner's Answer, mailed November 2, 2017 ("Ans.");
and the Final Office Action, mailed March 27, 2017 ("Final Act."), from
which this Appeal is taken.
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Application 14/692,959
Figure 4 of Klein is a block diagram of the XLAT translation device. Klein
,r 29. As shown, the XLAT translation device (38) includes a control unit
(58) and a translation table (XT) (54) "that may store data relating to how
frequently a particular virtual memory address and/or physical memory
address are accessed, and may store data that identifies a type of the memory
device that corresponds with each physical memory address." Klein ,r 29.
The LRU (least recently used) column (64) indicates how frequently a
physical memory address is accessed. Klein ,r 30. Klein discloses the LRU
field may be used (for example, by the control unit (56)) to identify if table
entries should be moved from the XT table to the TLB-i.e., if they are very
frequently accessed. Klein ,r 30. Klein's TLB contains similar fields (i.e.,
virtual address, physical address, LRU, and TYPE) to the XT table. See
Klein ,r,r 26-27, Fig. 3.
In rejecting claim 1, the Examiner finds Klein's translation lookaside
buff er discloses the claimed mapping circuitry and the XLA T translation
device discloses the claimed hint generating circuitry. Final Act. 3--4.
Further, the Examiner finds the LRU and TYPE fields in the XT table (54)
disclose the claimed hint data. Final Act. 3--4. In particular, the Examiner
explains,
it is understood from this that the modification of the LRU data would
provide indication that the entries of the XLAT table with the highest
values of LRU have been moved into the TLB, reading on the
limitation of hint data reflecting entries loaded into the mapping
circuitry; similarly, when entries are evicted from the TLB, Klein
discloses that "rows 44 that have been accessed with the least
frequency (e.g.[,] have the lowest value stored in the LRU column
50), may be removed from the table 42."
Final Act. 4.
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Appellants assert that neither Klein's LRU column nor TYPE column
discloses hint data indicating mapping data entries that have been loaded
into, or evicted from, the mapping circuity. App. Br. 9 ( emphasis omitted).
Appellants contend the TYPE column merely identifies a type of device
associated with the physical memory address and provides no disclosure of
the claimed hint data. App. Br. 9. Additionally, Appellants argue the LRU
column also fails to provide the claimed hint data and only identifies
candidate entries that may be moved from the XT table to the TLB. App.
Br. 9--10. Appellants assert identifying candidate entries does not disclose
data entries that have been loaded to the TLB. App. Br. 10. Similarly,
Appellants assert the LRU may be used to identify candidate entries to be
evicted from the TLB, but does not disclose that have been evicted. App.
Br. 11.
In response, the Examiner interprets the claim language of mapping
data entries "that have been loaded" into the TLB and "that have been
evicted" from the TLB as "incidental events." Ans. 3. The Examiner
further explains "the phrase 'have been loaded' only requires that at some
point in time, the entries were loaded into the TLB." Ans. 4. Additionally,
the Examiner states that, based on the LRU information, "one can trace this
entry" to know when to load the entry in the TLB. Ans. 4. Similarly, the
Examiner finds that "looking at the LRU information would provide insight
to why the entries were evicted from the TLB." Ans. 4.
When construing claim terminology during prosecution before the
Office, claims are to be given their broadest reasonable interpretation
consistent with the Specification, reading claim language in light of the
Specification as it would be interpreted by one of ordinary skill in the art.
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In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004).
However, the broadest reasonable interpretation differs from the broadest
possible interpretation. In re Smith Int'!, Inc., 871 F.3d 1375, 1383 (Fed.
Cir. 201 7); see also MPEP § 2111 ("The broadest reasonable interpretation
does not mean the broadest possible interpretation. Rather, the meaning
given to a claim term must be consistent with the ordinary and customary
meaning of the term (unless the term has been given a special definition in
the specification), and must be consistent with the use of the claim term in
the specification and drawings."). The correct inquiry in giving a claim term
its broadest reasonable interpretation in light of the specification is "an
interpretation that corresponds with what and how the inventor describes his
invention in the specification, i.e., an interpretation that is 'consistent with
the specification."' Smith, 871 F.3d at 1382-83 (quoting In re Morris, 127
F.3d 1048, 1054 (Fed. Cir. 1997)). We are mindful, however, that
limitations are not to be read into the claims from the Specification. In re
Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993).
We agree with Appellants (see Reply Br. 3-9) that the Examiner's
interpretation of the claim language is unreasonably broad in that it
improperly reads out claim limitations, is inconsistent with the Specification,
and renders the distinction of hint data (i.e., entries that have been loaded
versus those that have been evicted) meaningless, as "an evicted entry must
have 'at some point in time' been loaded to the TLB." Reply Br. 4--5.
"A claim is anticipated only if each and every element as set forth in
the claim is found, either expressly or inherently described, in a single prior
art reference." Verdegaal Bros., Inc. v. Union Oil Co. of Cal., 814 F.2d 628,
631 (Fed. Cir. 1987). Further, the principle of "inherency" requires that any
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information not expressly disclosed within a prior art reference would
nonetheless be known to be present in the subject matter of the reference,
when viewed by persons experienced in the field of the invention. However,
"anticipation by inherent disclosure is appropriate only when the reference
discloses prior art that must necessarily include the unstated limitation [ or
the reference] cannot inherently anticipate the claims." Transclean Corp. v.
Bridgewood Servs., Inc., 290 F.3d 1364, 1373 (Fed. Cir. 2002) (internal
citation omitted); In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999) (that a
feature in the prior art reference "could" operate as claimed does not
establish inherency).
Although the LRU information may be used to determine when
mapping data entries ought to be moved from the XT to the TLB ( or when
they should be evicted from the TLB), we agree with Appellants that the
cited portions of Klein relied upon by the Examiner do not disclose,
expressly or inherently, that the LRU information indicates that mapping
data entries have been loaded into, or evicted from, the TLB.
For the reasons discussed supra, and constrained by the record before
us, we do not sustain the Examiner's rejection of independent claim 1 under
35 U.S.C. § 102(a)(2). For similar reasons, we do not sustain the
Examiner's rejection of independent claims 19 and 20, which recite similar
limitations. Additionally, we do not sustain the Examiner's rejection of
claims 4--6, 9, 10, and 12-16, which depend directly or indirectly therefrom.
Claims 7, 8, 11, 17, and 18
Claims 7, 8, 11, 17, and 18 depend directly or indirectly from
independent claim 1 and were rejected under 35 U.S.C. § 103. The
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Examiner does not rely on the additionally cited references to address the
deficiencies related to the rejection of independent claim 1, discussed above.
Accordingly, we do not sustain the Examiner's rejections of claims 7, 8, 11,
17, and 18 under 35 U.S.C. § 103.
DECISION
We reverse the Examiner's decision rejecting claims 1, 4---6, 9, 10,
12-16, 19, and 20 under 35 U.S.C. § 102(a)(2).
We reverse the Examiner's decision rejecting claims 7, 8, 11, 17, and
18 under 35 U.S.C. § 103.
REVERSED
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