Ex Parte Blagodurov et al

Patent Trials and Appeals Board

Dec 20, 2018

14576912 - (D) (P.T.A.B. Dec. 20, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/576,912 12/19/2014 Sergey Blagodurov
109712 7590 12/25/2018
Advanced Micro Devices, Inc.
c/o Davidson Sheehan LLP
6836 Austin Center Blvd.
Suite 320
Austin, TX 78731
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1458-130568 8888
EXAMINER
VERDERAMO III, RALPH A
ART UNIT PAPER NUMBER
2136
NOTIFICATION DATE DELIVERY MODE
12/25/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@ds-patent.com
AMD@DS-patent.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SERGEY BLAGODUROV, MITESH RAMESH MESWANI,
GABRIEL H. LOH, MAURICIO BRETERNITZ JR.,
MARK RICHARD NUTTER, JOHN ROBERT SLICE,
DAVID ANDREW ROBERTS, MICHAEL IGNATOWSKI,
and MARK HENRY OSK.IN
Appeal2018-004122
Application 14/576,912
Technology Center 2100
Before MAHSHID D. SAADAT, JOHN P. PINKERTON, and
STEVEN M. AMUNDSON, Administrative Patent Judges.
SAADAT, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Final Rejection
of claims 1, 3-5, 7-15 and 17-19. 2 We have jurisdiction under 35 U.S.C.
§ 6(b ).
We reverse.
1 According to Appellants, the real party in interest is Advanced Micro
Devices, Inc. App. Br. 1.
2 Claims 2, 6, 16, and 20 have been previously canceled.
Appeal2018-004122
Application 14/576,912
STATEMENT OF THE CASE
Introduction
Appellants' disclosure is directed to processors and management of
multilevel memory hierarchies for processors. Spec. ,r 1. Claim 1, which is
illustrative of the invention, reads as follows:
1. A method comprising:
in response to a change in a phase of an application
executing at a processor:
selecting a range of memory locations of a multilevel
memory;
reorganizing data stored at the selected range of memory
locations based on a management mode of a first range of
memory locations different from the selected range of memory
locations;
transferring reorganized data stored at the selected range
of memory locations to the first range of memory locations; and
changing the management mode of the selected range of
memory locations.
The Examiner's Rejection
Claims 1, 3-5, 7-15, and 17-19 stand rejected under 35 U.S.C.
§ I03(a) as unpatentable over Ramanujan (US 2013/0268728 Al; Pub. Oct.
10, 2013) and Roberts (US 2014/0281149 Al; Pub. Sept. 18, 2014). See
Final Act. 3-21.
ANALYSIS
In rejecting claim 1, the Examiner finds Ramanujan discloses all the
recited elements of the claim, except for "in response to a change in a phase
of an application" and "changing the management mode of the selected
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Application 14/576,912
range of memory locations," for which the Examiner relies on paragraphs 15
and 25 of Roberts. See Final Act. 3-6. The Examiner further finds
paragraph 213 of Ramanujan discloses the recited steps of "reorganizing
data stored at the selected range of memory locations" and "transferring
reorganized data stored at the selected range of memory locations." See
Final Act. 4--5.
Appellants contend the Examiner's rejection is in error because
"Ramanujan and Roberts do not teach or suggest either transferring
reorganized data based on memory management modes concurrently
assigned to different memory locations or reorganizing data prior to
migration." App. Br. 5. Appellants cite different portions of Ramanujan in
paragraphs 78, 183-184, 194--195, and 213 and argue "Ramanujan merely
teaches flushing data out of the reassigned region; ' [ f]or example, if
software wishes to increase the size of the Direct Access mode region by
reducing the Write-Back Cache region, it may do so by first evicting and
invalidating the appropriate portion of the Near Memory Region' (emphasis
added). See Ramanujan, para. [0213]." Id. Additionally, Appellants argue
that the Examiner's statement that "the act of migrating or transferring
between two different memories inherently requires a reorganization of data
in order to be intelligible to the target memory" is not based on any evidence
or supported by the prior-art disclosure. App. Br. 7. 3
In response, the Examiner finds that the broadest reasonable
interpretation of the disputed claim limitation "doesn't explicitly require data
3 We do not address Appellants' other contentions because this contention is
dispositive of the issue on appeal.
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Appeal2018-004122
Application 14/576,912
to be reorganized prior to migration." Ans. 21. The Examiner further
explains:
Id.
[F]lushing the data from one memory to another inherently
requires some form of reorganization, in the broadest reasonable
interpretation of the term "reorganize". The data would now be
organized in a different location which is a reorganization.
Furthermore, if the memory of a different type there must be
some reorganization in order to be intelligible to the new
memory. The Roberts reference is then used to suggest that such
a reconfiguration may be in response to a change in the phase of
an application.
We disagree with the Examiner that the claimed stored data does not
need to be reorganized prior to migration. As stated by Appellants, "the
claim language clearly recites that it is the reorganized data that is
transferred, and therefore the data is necessarily reorganized based on a
memory management mode prior to migration of the reorganized data."
Reply Br. 3. As such, based on a review ofRamanujan, we are persuaded by
Appellants' contention that the Examiner has not explained how the change
in the configuration or flushing or cache regions meets the claimed steps of
"reorganizing data stored at the selected range of memory locations based on
a management mode of a first range of memory locations different from the
selected range of memory locations" and "transferring reorganized data
stored at the selected range of memory locations." As further pointed out by
Appellants (Reply Br. 3), "the mere act of data migration cannot be relied
upon to read upon the claim; the claim recites the features of reorganization
of data and the subsequent transferring of that reorganized data, and not
reorganization as the result of data migration." In other words, the Examiner
has not explained how the teachings of Ramanujan with respect to memory
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Application 14/576,912
storage configuration disclose reorganization of stored data prior to
transferring to a different range of memory locations.
Therefore, Appellants' arguments have persuaded us of error in the
Examiner's position with respect to the rejection of independent claim 1 and
independent claims 10 and 15, which recite similar limitations. We
therefore do not sustain the 35 U.S.C. § 103(a) rejection of claims 1, 10, and
15, as well as claims 3-5, 7-9, 11-14 and 17-19 dependent therefrom.
DECISION
We reverse the Examiner's decision to reject claims 1, 3-5, 7-15 and
17-19.
REVERSED
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