Ex Parte Birmiwal et al

Board of Patent Appeals and Interferences

Sep 27, 2010

10965628 (B.P.A.I. Sep. 27, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte PARAG BIRMIWAL and BERNARD CHARLES DRERUP
____________

Appeal 2009-007078
Application 10/965,628
Technology Center 2100
____________

Before HOWARD B. BLANKENSHIP, ST. JOHN COURTENAY III, and
STEPHEN C. SIU, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
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STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-7, 9-12, 15-18, and 20-22, which are all the claims
remaining in the application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.

Invention
Appellants’ invention relates to a system comprising a peripheral
component interface (PCI) host bridge. A voltage regulator is coupled to the
PCI host bridge and configured to regulate a signaling voltage based on a
received voltage indicator signal. See Abstract.

Representative Claims
1. A system, comprising:

a peripheral component interconnect (PCI) host bridge configured to
be coupled to a PCI bus, and to receive a system reset signal, to detect a PCI
operational mode of the PCI bus, and to generate a voltage indicator signal
based on the detected PCI operational mode; and

a voltage regulator coupled to the PCI host bridge and configured to
receive the voltage indicator signal and to regulate a signaling voltage for
the PCI bus based on the voltage indicator signal, wherein the PCI host
bridge is further configured to stabilize the voltage regulator prior to a
deassertion of the system reset signal.

9. A method, comprising:

receiving an asserted system reset signal;

generating a peripheral component interconnect (PCI) bus reset signal
based on the received system reset signal;
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determining a PCI operational mode of a PCI bus; and

stabilizing a voltage indicator signal based on the determined PCI
operational mode prior to a deassertion of the system reset signal.

Prior Art
Pathak US 5,936,444 Aug. 10, 1999
Miyazaki US 6,515,519 B1 Feb. 4, 2003
Lu US 6,760,574 B1 Jul. 6, 2004
Bacchus US 2005/0223246 A1 Oct. 6, 2005

Srinivasan US 7,073,078 B2 Jul. 4, 2006

PCI-X Protocol Addendum to the PCI Local Bus Specification
Revision 2.0a, p. 274 (2003).

Examiner’s Rejections
Claims 1-7, 9, 10, 12, 15, 16, and 18 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Srinivasan and Bacchus.
Claims 11 and 17 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Srinivasan, Bacchus, and PCI-X Protocol.
Claims 20-22 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Srinivasan, Bacchus, Pathak, Lu, and Miyazaki.

FINDINGS OF FACT
Srinivasan
Srinivasan describes a PCI system including a PCI-X Bridge 108 (Fig.
1) and a Power Control Unit 120. Bridge 108 provides a voltage indicator
(VIO) signal 112 and a power good (PGOOD) signal 114 to the Power
Control Unit. During system initialization, the PGOOD signal is asserted
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when the power voltages in the system are at an equilibrium state and
functional. With the information indicating whether a first or a second
operating voltage is to be provided, and whether the power voltages are
equilibrated, the Power Control Unit 20 provides the correct operating
voltage to a respective add-in card. Col. 2, l. 62 - col. 3, l. 15.

Bacchus
Bacchus teaches a procedure (Fig. 8) for initializing PCI slot circuitry
302 (Fig. 7) and a card 202.
The card 202 (Fig. 7) is held in reset (310; Fig. 8) as determined by a
reset signal 258 generated by System Management Entity 304. At the end of
the initialization procedure the System Management Entity releases the slot
circuitry 302 and card 202 from reset (330; Fig. 8). ¶¶ [0018], [0021],
[0029].

PRINCIPLES OF LAW
“What matters is the objective reach of the claim. If the claim extends
to what is obvious, it is invalid under § 103.” KSR Int’l Co. v. Teleflex, Inc.,
550 U.S. 398, 419 (2007). “The combination of familiar elements according
to known methods is likely to be obvious when it does no more than yield
predictable results.” Id. at 416.

ANALYSIS
Claims 9-12, 15-18, 21, 22
Independent claim 9 recites steps that include receiving an asserted
system reset signal, generating a PCI bus reset signal based on the received
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system reset signal, and stabilizing a voltage indicator signal prior to a
deassertion of the system reset signal. Independent claim 15 contains
language similar to that of claim 9. Claims 10-12 and 21 depend from claim
9. Claims 16-18 and 22 depend from claim 15.
The § 103(a) rejection applied against base claims 9 and 15 over
Srinivasan and Bacchus contends that Bacchus teaches generating a PCI bus
reset signal based on the received system reset signal depicted in Figure 7.
System management entity 304 (Bacchus Fig. 7), which may contain a
BIOS (¶ [0022]), generates a reset signal 258. From the drawings (e.g.,
Figs. 2 and 7), it appears that the reset signal distributed to the PCI cards
214, 216, and 202 is that generated by the system management entity. The
remainder of the disclosure, in particular paragraph [0029] of Bacchus,
appears to confirm that the only reset signal in the arrangement of Figure 7
is that generated by system management entity 304.
We therefore agree with Appellants that the evidence fails to support
the finding (e.g., Ans. 14) that Bacchus teaches that PCI-X Mode 2 Slot
Circuitry 302 (Fig. 7) generates a separate reset signal in response to the
system reset signal (system management entity reset signal), with this
second reset signal serving as the reset signal for the PCI-X cards.
As Appellants have demonstrated error in the rejection of claims 9
and 15, and the additional references applied against dependent claims do
not remedy the basis deficiency in the rejections, we do not sustain the
§ 103(a) rejections of claims 9-12, 15-18, 21, and 22.

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Claims 1-7 and 20
Claim 1 does not recite two separate reset signals, but a “system reset
signal.” Appellants argue that the combination of Srinivasan and Bacchus
fails to teach “wherein the PCI host bridge is further configured to stabilize
the voltage regulator prior to a deassertion of the system reset signal” as
claimed.
Appellants’ arguments in the Appeal Brief appear to be based, in the
main, on a requirement that claim 1 does not have. Claim 1 does not recite
or require a separate system reset signal and PCI bus reset signal. We
further observe that claim 1 does not require “stabilizing a voltage indicator
signal” as recited in claims 9 and 15.
We agree with the Examiner that reset signal 258 taught by Bacchus is
a “system reset signal” for all that claim 1 requires. We are not persuaded
by Appellants’ logic that Bacchus cannot be said to show the system reset
recited in claim 1 because Bacchus does not distinguish between a system
reset and a PCI bus reset.
Srinivasan discusses system initialization without using the word
“reset.” However, as we noted in the Facts section, Srinivasan teaches that
the Power Control Unit (i.e., voltage regulator) provides the correct
operating voltage after receiving a signal (PGOOD) from the PCI host
bridge, the signal indicating that the power voltages in the system are at an
equilibrium state and functional. As we also noted in the Facts section,
Bacchus teaches that PCI system components may be held in a reset state
during the entire initialization phase of the system.
We therefore agree with the Examiner that the collective teachings of
the references would have at least suggested that all the power voltages in
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the system be stable prior to deassertion of a system reset signal, such that
the PCI host bridge is “configured to stabilize the voltage regulator” prior to
deassertion of the signal, within the meaning of instant claim 1.
We thus sustain the § 103(a) rejection of claim 1. Dependent claims
2-7 and 20 fall with claim 1. See 37 C.F.R. § 41.37(c)(1)(vii).

DECISION
The rejection of claims 1-7, 9, 10, 12, 15, 16, and 18 under 35 U.S.C.
§ 103(a) as being unpatentable over Srinivasan and Bacchus is affirmed with
respect to claims 1-7 but reversed with respect to claims 9, 12, 15, 16, and
18.
The rejection of claims 11 and 17 under 35 U.S.C. § 103(a) as being
unpatentable over Srinivasan, Bacchus, and PCI-X Protocol is reversed.
The rejection of claims 20-22 under 35 U.S.C. § 103(a) as being
unpatentable over Srinivasan, Bacchus, Pathak, Lu, and Miyazaki is
affirmed with respect to claim 20 but reversed with respect to claims 21 and
22.

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).

AFFIRMED-IN-PART

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