Ex Parte Biles

Board of Patent Appeals and Interferences

Jun 4, 2009

10434367 (B.P.A.I. Jun. 4, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte STUART DAVID BILES
_____________

Appeal 2008-004383
Application 10/434,367
Technology Center 2100
______________

Decided:1 June 4, 2009
_______________

Before JOHN C. MARTIN, ST. JOHN COURTENAY III ,
and CAROLYN D. THOMAS, Administrative Patent Judges.

MARTIN, Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
(Continued on next page.)
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STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-8, 10-15, 17, 18, 20-33, and 35-38, which are all of the
pending claims. Claims 9, 16, 19, and 34 stand objected to for depending on
rejected claims.
We have jurisdiction under 35 U.S.C. § 6(b). We affirm and enter a
new ground of rejection under the enablement requirement of § 112, first
paragraph.

A. Appellant’s invention
Appellant’s Figure 1 is reproduced below.2

Mail Date (paper delivery) or Notification Date (electronic delivery).
2 The formal drawings submitted on August 29, 2003, replace the originally
filed informal drawings.
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Figure 1 is a schematic block diagram of a data processing apparatus in
which embodiments of the present invention may be employed.
Specification 15:8-9. The data processing apparatus 10 includes a number
of functional units 50, which, in the particular example of Figure 1, comprise
a load-store unit (LSU) 52, an arithmetic logic unit (ALU) 54, a multiplier
logic unit (MUL) 56, a floating point unit (FPU) 58 and a prefetch unit 59.
Id. at 15:9-12. An instruction cache 70 is provided for storing instructions
required by the various functional units 50. Id. at 15:12-13.
A register bank 30 is provided for storing data values to be
manipulated by the instructions executed on the functional units 50. Id. at
15:18-19. When a functional unit 50 is to execute an instruction, it will
typically obtain the required operand data values from the register bank 30
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via an appropriate read port within the access ports 40. Id. at 15:25-27.
Similarly, any data value generated as a result of execution of that
instruction will typically be written back to a destination register within the
register bank 30 via an appropriate write port within the access ports 40. Id.
at 15:27-30.
The application discloses a number of embodiments (referred to by
Appellant as “examples” at pages 9 and 10 of the Brief) of using cache
registers in different functional units.
Figure 2, which shows a first embodiment, is reproduced below.

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Figure 2 illustrates an embodiment in which the multiplier unit 56 is
provided with a register cache 100 having one or more cache entries for
storing copies of items of architectural state contained within the register
bank 30, with the aim of reducing the demand on the read ports 210
associated with the register bank. Id. at 16:12-16. The multiplier unit 56 is
arranged to perform operations of the type (A x B) + C in order to produce
an accumulate result. Id. at 16:16-17. The destination register for the result
is typically the same as the source register containing the “C” operand such
that on each iteration of the operation the accumulate value is updated and
returned to the relevant register in the register bank. Id. at 16:17-20.
The control logic 20 includes register cache control logic 280, which
is arranged to monitor the operands of instructions being executed by the
multiplier unit 56 in order to determine which register number is being used
to hold the accumulate data value. Id. at 17:6-9. When the accumulate
register number has been identified by the register cache control logic 280, it
sends a control signal over path 282 to the register cache 100 to cause the
register cache to set a valid bit 260 within a cache entry of the register cache
and also to store within a tag portion 262 of that cache entry an identification
of the register number containing the accumulate value. Id. at 17:9-14.
Then, when the accumulate value is output from the adder 240 and routed
back over path 244 to one of the write ports 200 for storage of that
accumulate value within the destination register of the register bank, that
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accumulate value is also routed over path 246 into the data portion 264 of
the relevant cache entry. Id. at 17:14-17.
The next time a multiply-accumulate instruction is issued to the
multiply unit 56, compare logic 270 within the control logic 20 will compare
the tag value 262 within the register cache output over path 274 (assuming
the corresponding valid bit 260 indicates that the tag value is valid) with the
accumulate register number specified within the instruction and received
over path 272. Id. at 17:18-22. In the event of a match, a hit signal is then
output over path 276 to the multiplexer 250 to cause the multiplexer 250 to
output over path 252 at the appropriate time the operand C’, i.e., the
accumulate value stored within the data portion 264 of the register cache
entry. Id. at 17:22-25. When the result is generated, it is returned not only
to the register bank 30 but also to the register cache over path 246. Id. at
17:25-26.
Other figures show embodiments employing cache registers in other
functional units. In the Figure 4 embodiment, a register cache 110 is
provided within a load-store unit (LSU) 400 for storing a base address used
by the LSU 400 in the generation of an effective address (EA) for a load
operation. Id. at 20:16-16-19. In the Figure 6A embodiment, logic 650 is
provided within the prefetch unit 600 for use in combination with a register
cache 120 to seek to predict effective addresses for load instructions during
the prefetch operation. Id. at 23:24-27. In the Figure 7 embodiment, a
register cache 810 is provided within a floating point unit (FPU) 58 to
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enable local caching of floating point operands required by the FPU 58. Id.
at 28:11-13. In the Figure 8A embodiment, a register cache 130 is provided
within the prediction logic 910 of a prefetch unit 900 to enable prediction of
the target address for indirect branch instructions to be performed within the
prefetch unit 900. Id. at 31:8-11.

B. The claims
The independent claims before us are claims 1 and 26, which read:
1. A data processing apparatus, comprising:
a plurality of registers for storing items of architectural
state;
a plurality of functional units, each functional unit for
performing a processing operation with reference to at least one
of said items of architectural state;
at least one of said functional units having a register
cache associated therewith having one or more cache entries,
each cache entry for storing a copy of one of said items of
architectural state and a register identifier identifying the
register containing that item of architectural state; and
control logic for determining a subset of said items of
architectural state to be copied in said register cache, said
subset comprising at least one item of architectural state which,
having regard to the processing operation of the functional unit
with which said register cache is associated, is likely to be
referred to multiple times.

26. A method of accessing items of architectural state
within a data processing apparatus comprising a plurality of
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registers operable to store said items of architectural state, and a
plurality of functional units, each functional unit being operable
to perform a processing operation with reference to one or more
of said items of architectural state, the method comprising:
for at least one of said functional units, providing a
register cache associated therewith having one or more cache
entries;
determining a subset of said items of architectural state to
be copied in said register cache in dependence on the
processing operation of the functional unit with which said
register cache is associated; and

storing within each cache entry a copy of one of said
items of architectural state within the subset and a register
identifier identifying the register containing that item of
architectural state.
Claims App. to Br.

C. The references and rejections
The Examiner relies on the following references:

Nomura US 5,099,419 Mar. 24, 1992
Harrison et al. (“Harrison”) US 5,694,568 Dec. 2, 1997
Wilhelm et al. (“Wilhelm”) US 5,956,747 Sep. 21, 1999
David A. Patterson & John L. Hennessy, Computer Architecture -- A
Qualitative Approach (1996 ed.) at 392 (“Hennessy”).

Claims 1-8, 10-14, 20-22, 25-33, and 35-38 stand rejected under
35 U.S.C. § 102(b) for anticipation by Wilhelm.
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Claim 14 stands rejected under § 103(a) for obviousness over
Wilhelm in view of Hennessy.
Claims 15, 17, and 18 stand rejected under § 103(a) for obviousness
over Wilhelm in view of Nomura.
Claims 23 and 24 stand rejected under § 103(a) for obviousness over
Wilhelm in view of Harrison.
Regarding the § 102(b) rejection, Appellant argues the merits of only
independent claims 1 and 26. Consequently, claims 2-8, 10-14, 20-22, and
will be treated as standing or falling with claim 1, while claims 27-33 and
35-38 will be treated as standing or falling with claim 26. In re Young,
927 F.2d 588, 590 (Fed. Cir. 1991).

THE ISSUES
Appellant has the burden to show reversible error by the Examiner in
maintaining the rejection. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir.
2006) (“On appeal to the Board, an applicant can overcome a rejection by
showing insufficient evidence of prima facie obviousness or by rebutting the
prima facie case with evidence of secondary indicia of nonobviousness.”)
(quoting In re Rouffet, 149 F.3d 1350, 1355 (Fed. Cir. 1998)).
The principal issues raised by Appellant’s arguments (addressed infra)
are whether the Examiner erred by:
(1) Refusing to interpret particular elements of claims 1 and 26 in
accordance with 35 U.S.C. § 112, sixth paragraph; and
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(2) Finding that Wilhelm discloses “determining a subset of said
items of architectural state to be copied in said register cache . . . .”

WHETHER CLAIMS 1 AND 26 RECITE ELEMENTS THAT
MUST BE CONSTRUED IN ACCORDANCE WITH § 112, ¶ 6
Appellant argues that the “determining” and “storing” elements of
method claim 26 and the “control logic” of apparatus claim 1, which
performs “determining” and “storing” operations, must be construed in
accordance with § 112, ¶ 6 and thus as limited to the disclosed examples and
equivalents thereof. Br. 8-11.

A. Apparatus claim 1
Appellant argues that even though apparatus claim 1 does not recite
“means,” it should be construed as a “means plus function” claim because
the recited “control logic” does not constitute specific structure for
performing the associated recited functions. Id. at 8. Although Appellant
did not cite a decision as support for this position, we note that Watts v. XL
Systems, Inc., 232 F.3d 877, 880 (Fed. Cir. 2000) held that the presumption
that § 112, ¶ 6 does not apply to an apparatus claim element that recites a
function without reciting a “means” for performing that function can be
rebutted by showing that the claim element fails to recite sufficient structure
for performing that function.
The Examiner concluded that § 112, ¶ 6 is inapplicable because the
recited “control logic” constitutes specific structure:
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[C]ontrol logic is in fact a structure (a broadly claimed logical
structure) and, therefore, [claim 1] should not be viewed as
being in means-plus-function form. Specifically, the examiner
asserts that appellant, in claiming “control logic”, is intending
to broadly claim and cover at least one of: a general hardware
structure of any type, a general software structure of any type,
or a general hardware/software combination structure of any
type, as described above, so long as it operates in equivalent
fashion to the control logic claimed.
Answer 17. In our view, this interpretation of “control unit” appears to
include every type of apparatus that can be used to perform the claimed
function and thus supports Appellant’s position that the recited “control
logic” does not constitute specific apparatus. Even so, we do not agree that
§ 112 ¶ 6 applies. The reason is that the reasoning of Watts does not apply
during examination in the USPTO. During USPTO examination, an
apparatus claim element that recites a function without reciting either a
“means” or any specific structure for performing the function will be
interpreted as broad enough to encompass any and all structures that perform
that function rather than being given a narrower interpretation under § 112,
¶ 6. Ex parte Miyazaki, 89 USPQ2d 1207, 1215-17 (BPAI 2008)
(precedential3).4

3 The precedential status of this decision is noted at
http://www.uspto.gov/web/offices/dcom/bpai/prec.htm (last visited May 29,
2008).
4 In accordance with Miyazaki, we are also entering a new ground of
rejection of claims 1-25 under the enablement requirement of § 112, first
(Continued on next page.)
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For the foregoing reasons, Appellant has not shown that the Examiner
erred by refusing to interpret the “control logic” recited in apparatus claim 1
as limited to the disclosed structure for performing the recited “determining”
function and equivalent structure in accordance with § 112, ¶ 6.

B. Method claim 26
Appellant has not explained why the “determining” and “storing”
elements of method claim 26 should be construed in accordance with § 112,
¶ 6, instead apparently relying on the fact that the language employed in
those elements is similar to the functional language recited in apparatus
claim 1. Br. 10-11. However, even if we had agreed with Appellant that the
“control unit” element of apparatus claim 1 should be interpreted in
accordance with § 112, ¶ 6, it would not necessarily follow that such
treatment should also apply to method claim 26. See O.I. Corp. v. Tekmar
Co., 115 F.3d 1576, 1583 (Fed. Cir. 1997) (“[E]ven if we were to hold that
the word ‘passage’ in the apparatus claims meets the section 112, ¶ 6, tests,
we would not agree with Tekmar that the ‘parallelism’ of the claims means
that the method claims should be subject to the requirements of section 112,
¶ 6. Each claim must be independently reviewed in order to determine if it is
subject to the requirements of section 112, ¶ 6.”).

paragraph, infra.
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Claim 26 does not employ the term “step” or “steps,” let alone the
“steps for” language that signals the drafter’s intent to invoke § 112, ¶ 6.
See Masco Corp. v. United States, 303 F.3d 1316, 1326 (Fed. Cir. 2002)
(“[I]n the context of method claims, the use of the term ‘steps for’ signals
the drafter's intent to invoke § 112, paragraph 6.”). Furthermore, “where a
method claim does not contain the term 'step[s] for,' a limitation of that claim
cannot be construed as a step-plus-function limitation without a showing that
the limitation contains no act." Id. Appellant has not explained why the
“determining” and “storing” elements should be understood to be reciting
functions rather than acts.
Consequently, Appellant has not shown that the Examiner erred in
refusing to interpret the “determining” and “storing” elements of method
claim 26 as limited to particular disclosed acts and equivalents thereof in
accordance with § 112, ¶ 6.

WHETHER WILHELM DISCLOSES “DETERMINING A
SUBSET OF SAID ITEMS OF ARCHITECTURAL STATE
TO BE STORED IN SAID REGISTER CACHE”
As explained below, Appellant also appears to be arguing that
Wilhelm fails to disclose “determining a subset of said items of architectural
state to be copied in said register cache,” as required by claims 1 and 26.
The claim terms “determining” and “subset” are not defined in the
Specification and therefore must be interpreted as broadly as is reasonable
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and consistent with the specification. In re Thrift, 298 F.3d 1357, 1364
(Fed. Cir. 2002).5
Wilhelm discloses a processor having distributed register caches and
employing a cache coherency protocol for maintaining coherency among the
register values in the distributed register cache. Wilhelm, col. 1, ll. 16-19.

5 Appellant’s above-discussed argument under § 112, ¶ 6 regarding claim 1
concerns whether to limit the recited “control logic” element to the disclosed
structure for performing the “determining” function attributed thereto and
equivalents thereof; it does not concern the interpretation of the functional
language itself. See Johnston v. IVAC Corp., 885 F.2d 1574, 1580 (Fed. Cir.
1989) (“Section 112 ¶ 6 can never provide a basis for finding that a means-
plus-function claim element is met literally where the function part of the
element is not literally met in an accused device.”). Similarly, insofar as
method claim 26 is concerned, even assuming for the sake of argument that
the “determining” and “storing” elements recite functions rather than acts,
the § 112, ¶ 6 argument concerns which acts are covered by the claimed
functions rather than meaning of the functional language.
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Wilhelm’s Figure 3 is reproduced below.

Figure 3 shows a block diagram of a processor having distributed
register caches according to Wilhelm’s invention. Id. at col. 4, ll. 63-65.
The processor 100 includes an instruction cache 12, a prefetch unit 14,
an instruction buffer 16, a dispatch unit 18, and a processing unit 20
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(dashed-line box) comprising a number of pipelines 26a through 26z. Id. at
col. 4, l. 65 to col. 5, l. 1. The processor 100 also includes a memory
hierarchy 24 including a register file 28, a data cache 30, main memory 32,
and disk storage 34. Id. at col. 5, ll. 1-4. The Examiner reads the recited “a
plurality of registers for storing items of architectural state” on register file
28 and reads the recited “functional units” on the pipelines. Final Action 3.
The processing unit 20 in the processor 100 also includes a plurality
of distributed register caches 102a through 102z associated with pipelines
26a through 26z, respectively. Wilhelm, col. 5, ll. 12-14. The Examiner
reads the recited “register cache” on one of these distributed register caches.
Final Action 3. An interconnect 108 is coupled between each of the register
caches 102 and the memory containing the register file 28. Wilhelm, col. 5,
ll. 15-17.
A plurality of local bypass logic circuits 110a through 110z are also
associated with each pipeline 26a through 26z, respectively. Id. at col. 5, ll.
28-30. Each local bypass unit 110 is responsible for passing recomputed
register values in the associated pipeline 26 to a younger instruction entering
the same pipeline 26. Id. at col. 5, ll. 30-32.
The processor 100 requires the use of a coherency protocol for
maintaining coherency among the register values in the pipelines 26a
through 26z. Id. at col. 5, ll. 38-40. Wilhelm developed a “one-copy”
protocol for the distributed register caches. Id. at col. 5, ll. 60-62. In the
one-copy protocol, only one addressable copy of a register value is allowed
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to exist in all the register caches 102 and in the register file 28 (or the
backing store copy) at a time. Id. at col. 5, l. 66 to col. 6, l. 2. If the register
cache 102a has a valid copy of a register value R, then a valid and
addressable copy of the register value R cannot exist in the register file 28,
or another one of the register caches 102b through 102z. Id. at col. 6, ll. 2-5.
Figure 4 is reproduced below.

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Figure 4 shows a table 130, residing in dispatch unit 18, for
implementing the one-copy protocol. Id. at col. 6, ll. 6-10. The table
includes entries 132(1) through 132(m), where (m) equals the number of
register values in the register file 28. Id. at col. 6, ll. 10-12. Each entry 132
includes a first storage location 134 for storing a register value identifier R(1)
through R(m), a second set of storage locations 136a through 136z, each
corresponding to the register caches 102a through 102z respectively, and a
third storage location 138 implicitly corresponding to the register file 28 (or
other backing store memory). Id. at col. 6, ll. 12-18. For each entry 132(1)
through 132(m), one of the storage locations 136a through 136z and 138 is set
to identify where the single valid and addressable copy of the of the register
resides in the processor 100. Id. at col. 6, ll. 18-21. The Examiner reads the
recited “control logic” of claim 1 on this table (Final Action 3) in
combination with dispatch unit 18, where it is located and maintained
(column 6, lines 8-10). Final Action 16. As support for this position, the
Examiner found that “Microsoft Press Computer Dictionary, Third Ed.
defines control unit as, ‘a device or circuit that performs an arbitrating or
regulating function’” and that “[o]ne of ordinary skill in the pertinent art
would have recognized that a dispatch unit clearly meets this definition.” Id.
Regarding the requirement of claims 1 and 26 for “determining a
subset of said items of architectural state to be copied in said register
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cache,”6 the Examiner found that one of ordinary skill would have
recognized that Wilhelm's register cache is smaller than the actual register
file (28) and that therefore “it is clearly evident that the register cache of
Wilhelm will only hold a subset of the architectural registers.” Final Action
17. More particularly, the Examiner explained:
Any value that is needed and is in the register file will be
brought into the register cache. Though the examiner agrees
that Wilhelm will bring in every value that will be used by the
processor into the register cache, this is not unlike the known
definition of a cache in the art, and the examiner maintains that
the register cache will only contain a subset of the architectural
state at any one time.
Id.
Appellant, citing the Examiner’s above-quoted statement, argues that
[t]he placing of all three operands A, B and C into the cache is
the direct opposite of the claimed invention (“control logic for
determining a subset of said items of architectural state”). The
inventor recognized that the greatest benefit comes from
caching the register holding the accumulate value, and it is this
register that the control logic identifies as the one to be cached
(see page 17, lines 7-17). Thus Wilhelm clearly would lead one
of ordinary skill away from the claimed invention and thus it
“teaches away” from the claimed construction and method.

6 Claim 26 adds that this “determining” is made “in dependence on the
processing operation of the functional unit with which said register cache is
associated.” Claim 1, on the other hand, more particularly specifies that the
determined subset “compris[es] at least one item of architectural state which,
having regard to the processing operation of the functional unit with which
said register cache is associated, is likely to be referred to multiple times.”
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Br. 15-16. Because claims 1 and 26 stand rejected for anticipation (as to
which a “teaching away” argument is not relevant), we understand
Appellant’s position to be that Wilhelm does not disclose “determining a
subset of said items of architectural state to be copied in said register cache.”
We are unpersuaded by this argument because the claim language does not
preclude the storage of three operands. To the contrary, the claims permit
storage of plural operands by specifying that the stored subset comprises “at
least one item of architectural state.” Consequently, Appellant has not
shown that the Examiner erred in finding that Wilhelm discloses the
“determining” limitation of claim 26.
Regarding the further requirement of claim 1 that the stored subset of
architectural states “compris[e] at least one item of architectural state which
. . . is likely to be referred to multiple times,” the Examiner cited Wilhelm’s
disclosure in column 3, lines 29-32 that “[e]ach register cache stores register
values that were just used or will soon be needed by the instructions that
have or will be executed on the pipeline associated with the register cache”
(emphasis added). Answer 20. Specifically, citing “[a] concept known in
the art is the ‘locality of reference’ or ‘principle of locality,’” the Examiner
found that “Wilhelm caches registers that were just used because if they
were just used, then they are determined by the system to likely be referred
to multiple times in the near future.” Id. The Examiner additionally relies
on Wilhelm’s discussion of cache replacement strategies in column 10, lines
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1-8. Id. at 20-21. Appellant, who did not file a Reply Brief, has not pointed
out any error in the above reasoning of the Examiner.
For the foregoing reasons, Appellant has not shown error in the
Examiner’s finding that the Wilhelm satisfies the “determining a subset of
said items of architectural state to be copied in said register . . .” limitations
of claims 1 and 26.

WHETHER THE EXAMINER HAS ESTABLISHED ANY MOTIVATION
FOR COMBINING THE REFERENCE TEACHINGS
Appellant’s argument (Br. 14-15) that the Examiner has not
established any motivation for combining the reference teachings in a way
that cures the deficiencies of Wilhelm with respect to claims 1 and 26 is
unpersuasive because those claims are rejected only for anticipation by
Wilhelm and because Appellant has not established that Wilhelm fails to
satisfy all of the limitations of those claims.
For the same reason, we are unpersuaded by the same argument (Br.
17-21) as directed to claims 14, 15, 17, 18, 23, and 24, which stand rejected
for obviousness over Wilhelm in combination with one or more of the other
references. That is, regarding these claims Appellant argues only that the
Examiner has not established any motivation for combining the reference
teachings in a way that cures alleged deficiencies of Wilhelm with respect to
claims 1 and 26.

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DECISION
The Examiner’s rejection of claims 1-8, 10-14, 20-22, 25-33, and 35-
38 under U.S.C. § 102(b) for anticipation by Wilhelm is affirmed, as are the
rejection of claim 14 under § 103(a) for obviousness over Wilhelm in view
of Hennessy, the rejection of claims 15, 17, and 18 under § 103(a) for
obviousness over Wilhelm in view of Nomura, and the rejection of claims 23
and 24 under § 103(a) for obviousness over Wilhelm in view of Harrison.

NEW GROUND OF REJECTION
Pursuant to our authority under 37 C.F.R. § 41.50(b), we are hereby
rejecting claims 1-25 under 35 U.S.C. § 112, first paragraph (enablement
requirement) because, as explained above, the recited “control logic” of
claim 1 is broad enough to encompass any and all structures capable of
performing the associated “determining” function and thus lacks an enabling
disclosure with respect to its full scope. See Miyazaki, 89 USPQ2d at 1217
(“[W]hen the [claim] limitation encompasses any and all structures or acts
for performing a recited function, including those which were not what the
applicant had invented, the disclosure fails to provide a scope of enablement
commensurate with the scope of the claim and the claim would violate the
prohibition of Halliburton [Oil Well Cementing Co. v. Walker, 329 U.S. 1
(1946)]”). Dependent claims 2-25 do not recite specific structure for the
“control logic” of claim 1.

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APPELLANT’S OPTIONS FOR RESPONDING TO
THE DECISION AND NEW GROUND OF REJECTION
Regarding the affirmed rejection(s), 37 C.F.R. § 41.52(a)(1) (2008)
provides that "Appellant may file a single request for rehearing within two
months from the date of the original decision of the Board" (emphasis
added). The date of the decision appears in the caption at page 1.
Regarding the new ground of rejection pursuant to 37 C.F.R.
§ 41.50(b), that paragraph explains that "[a] new ground of rejection
pursuant to this paragraph shall not be considered final for judicial review."
Appellant, within two months from the date of this decision, must exercise
one of the following two options with respect to the new ground of rejection
to avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the Examiner, in which event the proceeding
will be remanded to the Examiner. . . .
(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same record. . . .
37 C.F.R. § 41.50(b) (2008).

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§§ 41.50(f) and 41.52(b).

AFFIRMED; 37 C.F.R. § 41.50(b)

KIS

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