13251987 (P.T.A.B. Mar. 30, 2016)

Ex Parte BERNIER et al

Patent Trial and Appeal BoardMar 30, 2016

13251987 (P.T.A.B. Mar. 30, 2016)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/251,987 10/03/2011 WILLIAM E. BERNIER YOR920110317US1 (14-33) 6698 68397 7590 03/31/2016 THE LAW OFFICES OF ROBERT J. EICHELBURG HODAFEL BUILDING, SUITE 200 196 ACTON ROAD ANNAPOLIS, MD 21403 EXAMINER VUONG, THAI T ART UNIT PAPER NUMBER 2829 MAIL DATE DELIVERY MODE 03/31/2016 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ________________ Ex parte WILLIAM E. BERNIER, BING DANG, MARIO J. INTERRANTE, JOHN U. KNICKERBOCKER, and SON K. TRAN ________________ Appeal 2014-007676 Application 13/251,987 Technology Center 2800 ________________ Before CAROLYN D. THOMAS, JEREMY J. CURCURI, and JOHN R. KENNY, Administrative Patent Judges. CURCURI, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1–14. App. Br. 1. We have jurisdiction under 35 U.S.C. § 6(b). Appeal 2014-007676 Application 13/251,987 2 Claims 1–3, 5, 7–11, and 13 are rejected under 35 U.S.C. § 103(a) as unpatentable over Cho (US 2010/0244223 A1; Sep. 30, 2010) and Lee (US 2005/0046002 A1; Mar. 3, 2005). Final Act. 2–6. Claim 4 is rejected under 35 U.S.C. § 103(a) as unpatentable over Cho, Lee, and Joshi (US 7,439,613 B2; Oct. 21, 2008).Id. 6–7. Claim 6 is rejected under 35 U.S.C. § 103(a) as unpatentable over Cho, Lee, and Joshi (US 2011/0233748 A1; Sep. 29, 2011).Id. 7–8. Claims 12 and 14 are rejected under 35 U.S.C. § 103(a) as unpatentable over Cho, Lee, and Morrison (US 7,709,915 B2; May 4, 2010).Id. 8–10. We affirm. STATEMENT OF THE CASE Appellants’ invention relates to “miniaturization of electronics through 3D packaging structures incorporating integrated circuit devices protected against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC).” Spec. ¶ 1. Claim 1 is illustrative and reproduced below: 1. An interposer sandwich structure article of manufacture comprising a top interposer and a bottom interposer enclosing an integrated circuit electronic device, an attaching structure for attaching said device to said bottom interposer, and an interconnection structure connecting said top interposer to said bottom interposer, said bottom interposer including through silicon via interconnects that connect a chip carrier under said bottom interposer to said integrated circuit electronic device. Appeal 2014-007676 Application 13/251,987 3 ANALYSIS THE OBVIOUSNESS REJECTION OF CLAIMS 1–3, 5, 7–11, AND 13 OVER CHO AND LEE The Examiner finds the combined teachings of Cho and Lee teach all limitations of claim 1. Final Act. 2–4. The Examiner relies on Cho for all limitations of claim 1, except for the recited (claim 1) “bottom interposer including through silicon via interconnects that connect a chip carrier under said bottom interposer to said integrated circuit electronic device,” for which the Examiner relies on Lee. Id. at 4. The Examiner reasons: It would have been obvious to one of ordinary skill in the art at the time the invention was made to incorporate the well- known features disclosed by Lee into the teaching of Cho. One would be motivated to provide an integrated circuit packaging system with reducing costs, and better performance. Id. Appellants present the following principal arguments: i. “[T]he Examiner has not pointed to anything in the cited references that would lead a person with ordinary skill in the art to combine their teachings.” App. Br. 6. ii. “Cho, however neither teaches nor suggests nor describes substrate 202 as an ‘interposer.’ The August 1, Office communication does this by re-numbering and re-naming structure 202 as ‘interposer 106B’[].” Id. at 9; see also Reply Br. 3–4. iii. “[T]he [E]xaminer’s ‘interpose BT’ is in fact Lee’s element 11a defined by Lee in his written description as a transistor, not an ‘interposer.’” App. Br. 12; see also Reply Br. 4–5. iv. “Even if the Board would consider Lee’s transistor 11a as an interposer, contrary to the foregoing analysis, combining Cho and Lee would Appeal 2014-007676 Application 13/251,987 4 result in substituting Lee’s ‘transistor’ 11a for Cho’s ‘substrate’ 202 without explaining why the skilled artisan would be motivated to do so.” App. Br. 14; see also Reply Br. 6–7. We do not see any errors in the Examiner’s findings. Nor do we see any error in the Examiner’s legal conclusion of obviousness. Regarding the term “interposer,” the Examiner’s findings are consistent with the broadest reasonable interpretation of that term in light of the disclosure. The Specification does not define the term “interposer” but does describe (Spec. ¶ 6 (emphasis added)): In one embodiment, this innovative idea provides for ESD, EMI and EMC shielding and protection of integrated circuit devices in 3D packaging by creating a sandwich of interposers around the integrated circuit device in which metallized shielding and diode protective devices may be incorporated into both the top and bottom interposers. We find the plain meaning of “interpose” in the pertinent sense is: “1 a : to place in an intervening position.” MERRIAM-WEBSTER’S COLLEGIATE DICTIONARY 612 (10TH ED. 1997). Thus, we find the broadest reasonable interpretation of “interposer” includes a structure located in an intervening position. This interpretation does not preclude the Examiner’s findings, adopted by us below. For example, we agree with and adopt as our own the Examiner’s explanation regarding the annotations that Appellants challenge: The annotations are to clearly show the prior art features that match the claimed limitations and to make the office action more easily understandable. Even with different labels or names, the annotated features (AT: attach structure; 106B, BT: bottom interposer) can perform [the] same function as claimed attaching structure and bottom interposer, respectively. Ans. 3. Appeal 2014-007676 Application 13/251,987 5 Regarding argument ii, this argument does not show any error in the Examiner’s findings. We agree with and adopt as our own the Examiner’s explanation: “The [E]xaminer considers Cho’s substrate 202 to be an interposer because it is in between and connected to the external interconnects 206 and the integrated circuit 224 (see Cho fig. 2 and paragraph [0064]).” Ans. 3. Regarding argument iii, this argument does not show any error in the Examiner’s findings. Lee’s transistor 11a is an interposer because it is in between and connected to device 11 and carrier 31. See Lee Fig. 3. Regarding arguments i and iv, these arguments do not show any error in the Examiner’s findings or conclusion of obvious because the Examiner has provided an articulated reasoning with a rational underpinning to support the Examiner’s conclusion — we agree with and adopt as our own the Examiner’s explanation: “One would be motivated to provide an integrated circuit packaging system with reduced costs where the chip carrier can be re- used and incorporated to support and protect the chip packages for better performance.” Ans. 4. We, therefore, sustain the Examiner’s rejection of claim 1, and of claims 2, 3, 5, 7–11, and 13, which depend from claim 1 and are not separately argued. THE OBVIOUSNESS REJECTIONS OF CLAIMS 4, 6, 12, AND 14 OVER VARIOUS COMBINATIONS INCLUDING CHO, LEE, JOSHI ‘613, JOSHI ‘748, AND/OR MORRISON Appellants present no arguments pertaining to the Examiner’s obviousness rejections of claims 4, 6, 12, and 14. See App. Br. 3–16. Appeal 2014-007676 Application 13/251,987 6 Accordingly, we summarily sustain the rejections of claims 4, 6, 12, and 14 at least for reasons discussed above with respect to claim 1. See Manual of Patent Examining Procedure (MPEP) § 1205.02, 8th ed., Rev. 8, July 2010 (“If a ground of rejection stated by the examiner is not addressed in the Appellant’s brief, that ground of rejection will be summarily sustained by the Board.”). DECISION The Examiner’s decision rejecting claims 1–14 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1). AFFIRMED