Ex Parte Benhase et al

Patent Trial and Appeal Board

Jun 23, 2016

13842520 (P.T.A.B. Jun. 23, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/842,520
78650 7590
Nelson and Nelson
775 High Ridge Drive
Alpine, UT 84004
03/15/2013
06/27/2016
FIRST NAMED INVENTOR
Michael Thomas Benhase
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TUC920110130US2 3729
EXAMINER
VILLANUEVA, LEANDRO R
ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
06/27/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
dan@nnpatentlaw.com
alexis@nnpatentlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL THOMAS BENHASE, LOKESH MOHAN GUPTA,
and MATTHEW JOSEPH KALOS
Appeal2015-001839
Application 13/842,520
Technology Center 2100
Before CATHERINE SHIANG, KAMRAN JIVANI, and
MATTHEW J. McNEILL, Administrative Patent Judges.
JIVANI, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 seek our review under 35 U.S.C. § 134(a) of the
Examiner's final decision rejecting claims 1-7, which are all the claims
pending in the present patent application. We have jurisdiction under
35 U.S.C. § 6(b).
We AFFIRM.
1 Appellants identify International Business Machines Corporation as the
real party in interest. App. Br. 2.
Appeal2015-001839
Application 13/842,520
STATEMENT OF THE CASE
The present application relates to caching data in tiered storage
architectures. Spec. i-f 1.
Claim 1 is illustrative (disputed limitations emphasized):
1. A method for improving the efficiency of a
tiered storage architecture comprising at least three
storage tiers, the method comprising:
providing first, second, and third storage
tiers, wherein the first storage tier acts as a cache for
the second storage tier, and the second storage tier
acts as a cache for the third storage tier;
using, in the first storage tier, a first cache
line size corresponding to an extent size of the
second storage tier;
using, in the second storage tier, a second
cache line size corresponding to an extent size of the
third storage tier, wherein the second cache line size
is larger than the first cache line size;
maintaining, in the first storage tier, a first
cache directory indicating which extents from the
second storage tier are cached in the first storage
tier, the first cache directory containing first cache
directory entries of a first size; and
maintaining, in the first storage tier, a second
cache directory indicating which extents from the
third storage tier are cached in the second storage
tier, the second cache directory containing second
cache directory entries of a second size different
from the first size.
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Appeal2015-001839
Application 13/842,520
The Rejections
Claims 1-7 stand provisionally rejected for obviousness-type double
patenting over claims 8-14 of co-pending Application No. 13/367,155.
Claims 1---6 stand rejected under 35 U.S.C. § 103(a) over Raz
(US 6,311,252 Bl; Oct. 30, 2001) and Caprioli et al. (US 2009/0204761 Al;
Aug. 13, 2009).
Claim 7 stands rejected under 35 U.S.C. § 103(a) over Raz, Caprioli,
and Zheng et al., IEEE International Symposium on Performance Analysis
for Systems and Software.
ANALYSIS
Obviousness
Based on Appellants' arguments, we decide the appeal on the basis of
representative claim 1. See 37 C.F.R. § 41.37(c)(l)(iv) (2012).
Appellants contend the Examiner errs because "the Examiner fails to
point to any portions of Caprioli that teach a multi-stage cache directory
(i.e., first and second cache directories), where each of the cache directories
contains cache directory entries of a different size." Reply Br. 2; App. Br. 7.
Appellants further contend that the cited references fail to teach or suggest
that "both the first and second cache directories reside in the 'first storage
tier."' Reply Br. 3.
We have considered Appellants' arguments in the Appeal Brief and
Reply Brief, as well as the Examiner's Answer thereto. We are not
persuaded by Appellants' arguments for at least the following reasons.
First, the Examiner finds the combination of Raz and Caprioli teaches
or suggests a multi-stage cache directory where each of the cache directories
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Appeal2015-001839
Application 13/842,520
contains cache directory entries of a different size, as claimed. Final. Act.
12; Ans. 4. The Examiner further finds, and we agree, the cited combination
would result in directories that
would also have to necessarily be of different size
in order to keep track of the entries as they move
from one level to the next because there would have
to be a 1-1 correspondence between the entries in
each level and the corresponding directory entry
which tracks their location. If such a 1-1
correspondence does not exist, a situation would
arise in which an entry in the level is not accounted
for by the directory, and the system would not work.
Ans. 4. Appellants do not rebut this finding. See Reply Br. 2-3.
Second, we are not persuaded by Appellants' argument regarding the
location ofRaz's cache index 22 and indexes 50. We agree with Appellants
that Figure 1 depicts cache index 22 within cache memory 20, and indexes
50 within system memory but outside cache memory 20---and thus we agree
this configuration does not literally recite the claim requirement that the first
and second cache directories each be within the first tier. Appellants do not
present, however, adequate evidence that Raz's configuration would not
suggest the claimed arrangement. Absent from Appellants' argument is
persuasive evidence that the arrangements resulting from the cited
combination would have been "uniquely challenging or difficult for one of
ordinary skill in the art." See Leapfrog Enters., Inc. v. Fisher-Price, Inc.,
485 F.3d 1157, 1162 (Fed. Cir. 2007).
Accordingly, on the record before us, we sustain the Examiner's 35
U.S.C. § 103(a) rejection of claim 1. Appellants present no further
arguments on claims 2-7. Accordingly, we sustain the Examiner's 35
U.S.C. § 103(a) rejections of claims 2-7.
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Appeal2015-001839
Application 13/842,520
Double Patenting
Claims 1-7 stand provisionally rejected on the ground of nonstatutory
obviousness-type double patenting over claims 8-14 of co-pending
Application No. 13/367155. Final Act. 2-7. Appellants fail to address this
provisional rejection. Arguments not made are considered waived. See 37
C.F.R. § 41.37(c)(l)(iv)(2012).
Accordingly, we sustain the Examiner's provisional nonstatutory
obviousness-type double patenting rejection of claims 1-7.
DECISION
We affirm the Examiner's decisions rejecting claims 1-7.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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