Ex Parte Bauerle

Patent Trial and Appeal Board

Jul 21, 2014

11052461 (P.T.A.B. Jul. 21, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte PAUL A. BAUERLE
____________

Appeal 2012-000926
Application 11/052,461
Technology Center 2600
____________

Before BRADLEY W. BAUMEISTER, DENISE M. POTHIER, and
JENNIFER L. McKEOWN, Administrative Patent Judges.
POTHIER, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1–13 and 15–20. Claim 14 has been canceled. App.
Br. 5. We have jurisdiction under 35 U.S.C. § 6(b). We affirm.

Invention
Appellant’s invention concerns a method and system for protectively
storing a variable from a pulse-width modulated (PWM) signal comprising
an input module that receives the PWM signal and measures times of rising
and falling edges of the PWM signal. A memory module has storage for
variables. An arithmetic module performs subtraction and division. A
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control module communicates with the input module, the memory module,
and the arithmetic module, and instructs the arithmetic module to calculate
an on-time, an off-time, a period, a duty cycle, and a complementary
percentage. The control module stores the duty cycle and the
complementary percentage in the memory module. See Abstract; Spec. ¶ 5.
Claim 11 is reproduced below with emphasis:
11. A method for protectively storing a variable from a pulse-width
modulated (PWM) signal, comprising:
determining at least two of an on period, an off period, and a total
period, of the PWM signal;
calculating a first parameter of interest from said at least two of
said on period, said off period, and said total period;
calculating a second parameter of interest from said at least two of
said on period, said off period, and said total period;
storing said first parameter and said second parameter;
retrieving stored values of said first parameter and said second
parameter at a later time;
performing a comparison of said stored value of said first
parameter and said stored value of said second parameter; and
selectively performing error handling based on said comparison.

The Examiner relies on the following as evidence of unpatentability:
DeVito US 4,904,921 Feb. 27, 1990
Soenen US 6,028,527 Feb. 22, 2000
Cooke US 6,366,070 B1 Apr. 2, 2002
Kizer US 6,967,514 B2 Nov. 22, 2005
(filed Oct. 21, 2002)

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The Rejections
Claims 1–6, 8, 11, 12, 15–17, and 19 are rejected under 35 U.S.C.
§ 103(a) as unpatentable over Soenen and DeVito. Ans. 4–9.
Claims 13 and 20 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Soenen, DeVito, and Kizer. Ans. 9–10.
Claims 7, 9, 10, and 18 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Soenen, DeVito, and Cooke. Ans. 10–12.

OBVIOUSNESS REJECTION OVER SOENEN AND DEVITO
Regarding independent claim 11, Appellant argues Soenen and
DeVito fail to teach “calculating a second parameter of interest from said at
least two of said on period, said off period, and said total period.” App.
Br. 11–12; Reply Br. 5–6. Appellant argues DeVito’s “duty cycle binary
signal 1-d,” which the Examiner maps to the second parameter, is not
calculated from the recited “at least two of said on period, said off period,
and said total period.” App. Br. 11–12. Appellant contends that DeVito
produces a second signal having a complementary duty cycle from the first
signal having a first duty cycle, rather than producing the second signal from
the first and second inputs. Reply Br. 6.
Appellant further argues that DeVito fails to teach “storing said first
parameter and said second parameter” recited in claim 11. App. Br. 12–14.
Specifically, Appellant argues there is no indication that Figure 3 stores the
signals received from the multipliers and this figure merely suggests
transmitting signals from the comparator to the multipliers. Appellant also
asserts that claim 11 requires retrieving the values at a later time and thus a
temporary passage of a signal between components cannot be considered
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storing as recited. App. Br. 13. Appellant further contends the signals being
transmitted from comparator 74 are not the duty cycles d and 1-d
themselves, but rather the binary signals being modulated by the duty cycles.
App. Br. 13 (citing DeVito 6:29–30); Reply Br. 6–8. Appellant also argues,
even if multipliers 58 and 80 included an input buffer, the input buffer
would not store the duty cycles d and 1-d but instead the square waves
having those duty cycles. App. Br. 13–14.
Lastly, Appellant argues DeVito fails to teach “selectively performing
error handling based on said comparison” recited in claim 11. App. Br. 14.
Specifically, Appellant argues simply accumulating an error signal is not
performing error handling. Id. Further, Appellant argues DeVito does not
teach performing the error handling “selectively.” Instead, Appellant argues
DeVito’s error handling is constant, because “integrator 92 operates without
exception on the output of the adder 90.” Id.

ISSUES
Under § 103, has the Examiner erred in rejecting claim 11 by finding
that Soenen and DeVito collectively teach:
(a) “calculating a second parameter of interest from said at least two
of said on period, said off period, and said total period”;
(b) “storing said first parameter and said second parameter”; and
(c) “selectively performing error handling based on said comparison”?

ANALYSIS
Based on the evidence of record, we find that the Examiner has not
erred in rejecting claim 11 based on Soenen and DeVito. Concerning the
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limitation, “calculating a second parameter of interest from said at least two
of said on period, said off period, and said total period,” the Examiner finds
that (1) Soenen discloses calculating a duty cycle which reads on the “first
parameter of interest” and (2) DeVito teaches obtaining a duty cycle, d, and
its complement, 1-d. Ans. 6–7 (citing DeVito 5:33–62, 6:61–7:12), 13
(citing DeVito 5:60–62, 6:61–68; Fig. 3). The Examiner maps this
complement of the duty cycle, 1-d, to the recited “second parameter of
interest” in claim 11. See id.
We agree with the Examiner that these passages teach and suggest the
recited “calculating” step and adopt the Examiner’s findings and reasons as
our own. See Ans. 13 (discussing how DeVito teaches obtaining a duty
cycle, d, and its complement, 1-d and citing DeVito 5:60–62, 6:61–68; Fig.
3). To elaborate, Appellant does not dispute that the mapped first parameter
(i.e., the duty cycle) is calculated from at least two of the on-period, the off-
period, and the total period. App. Br. 11–12. Appellant’s main contention is
that the calculating step of the second parameter in DeVito is not performed
independent of the first parameter calculation. App. Br. 11; Reply Br. 6.
Yet, claim 11 is not limited to a calculation independent of or without use of
the first parameter calculation.
As Appellant indicates (see App. Br. 12), DeVito teaches computing
the complement of the duty cycle (i.e., 1-d and the mapped second
parameter) using the duty cycle (i.e., d or the mapped first parameter). See
DeVito 5:60–62, 6:29–31. Because DeVito teaches that the complement of
duty cycle, 1-d, is calculated from the first parameter, DeVito suggests the
same variables used to calculate the first parameter are also used indirectly,
at a minimum, to calculate the second parameter. Thus, even though the
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second parameter in DeVito is calculated as the complement or inversion of
the first parameter (see DeVito 5:60–62), such a calculation ultimately relies
on at least two of the on-period, the off-period, and the total period, given
that the first parameter is calculated based on those inputs. Therefore,
DeVito teaches and suggests “calculating a second parameter of interest
from said at least two of said on period, said off period, and said total
period,” as broadly recited in claim 11.
Regarding the disputed limitation, “storing said first parameter and
said second parameter,” we adopt the Examiner’s findings and reasons as
our own. See Ans. 14. The Examiner takes the position that an ordinarily
skilled artisan would have recognized a multiplier needs memory to store
and submit values in order to perform its operations. Id. We agree. In order
to perform the multiplier functions on the input values (e.g., d and 1-d as
shown in Figure 3), DeVito suggests to an ordinarily skilled artisan storing
the values at least temporarily. Without storing these values, the multiplier
would not be able to obtain the values used to perform the necessary
calculations of a multiplier. See In re Preda, 401 F.2d 825, 826 (CCPA
1968) (noting that “in considering the disclosure of a reference, it is proper
to take into account not only specific teachings of the reference but also the
inferences which one skilled in the art would reasonably be expected to draw
therefrom”).
The Examiner further finds that it was known in the art to have
memory devices with a digital multiplier to store and submit multiplicand
values for the multiplication operation. Ans. 14. Appellant also suggests a
person of ordinary skill in the art would have recognized that the multipliers,
such as those in DeVito, can include an input buffer or some storage. See
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App. Br. 13; Reply Br. 7. Also, an ordinarily skilled artisan would have
recognized that these temporarily stored values are used later in time to
perform multiplier operations. See KSR Int’l Co. v. Teleflex Inc., 550 U.S.
398, 418 (2007) (noting that an obviousness analysis “can take account of
the inferences and creative steps that a person of ordinary skill in the art
would employ.”) Accordingly, DeVito teaches and suggests “storing said
first parameter and said second parameter” as recited in claim 11.
Appellant also argues any existing input buffer in DeVito would store
either a 0 or a 1 — not the duty cycles, d or 1-d —, because the signals are
binary signals and not the duty cycles. App. Br. 13–14; Reply Br. 7. We are
not persuaded. As explained above and by the Examiner, we find that
DeVito discloses “d” as the duty cycle and not just a binary signal. See
DeVito, Fig. 3 (upper right side of the figure with arrow between “d” and the
description “BINARY SIGNAL DUTY CYCLE”). Thus, the signal
represents the duty cycle. Additionally, the Examiner notes that “d” is
described in DeVito as the duty cycle of a binary signal having a value
between 0 and 1 and not just the value 0 or 1. See Ans. 15 (citing DeVito
6:27–30). Thus, when combined with the above discussion that a person of
ordinary skill in the art would have recognized multipliers include input
buffers or some temporary storage, we conclude that the duty cycle d and its
complement 1-d (i.e., the mapped first and second parameters) submitted to
the multipliers are stored as broadly recited in claim 11.
Lastly, Appellant asserts that Soenen and DeVito fail to teach or
suggest “selectively performing error handling based on said comparison.”
App. Br. 14. We agree with the Examiner that claim 11 does not require the
comparison to generate an error signal but only that error handling is
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performed based on the comparison. Ans. 16. Appellant challenges that
output 90 is an error signal and that integrator 92 performs error handling.
App. Br. 14. However, the Examiner states that the comparison results are
sent to a feedback loop formed by components 90, 92, and 94, which
collectively performs error handling and where the output signal from
converter 94 is coupled back to adder 90. Ans. 16 (citing Fig. 3); DeVito
7:1–5; Fig. 3. The Examiner even further states that feedback loops are
known by the ordinarily skilled artisan to perform “error handling to
minimize the difference between the input signal and the feedback signal.”
Ans. 16. Appellant does not challenge this later finding that feedback loops
perform error handling.
Appellant further does not dispute the Examiner’s finding that DeVito
teaches that there is a “user-selectable” value, Rscale, in the feedback loop
used to handle the error signal selectively. Ans. 16 (citing DeVito 7:1–12).
Based on this undisputed finding and given the broad language of claim 11,
we find the Examiner’s position reasonable that the ultimate results of the
error handling routine is performed “selectively.” Id. Accordingly, we find
that DeVito teaches or suggests “selectively performing error handling based
on said comparison” recited in claim 11.
For the foregoing reasons, Appellant has not persuaded us of error in
the rejection of independent claim 11.
Independent claims 1 and 16 recite similar limitations to those
disputed for claim 11. Appellant argues the rejection of these claims should
be reversed for at least the same reasons stated above with respect to claim
11. App. Br. 14–15. We are not persuaded for the above-explained reasons.
Dependent claims 2–6, 8, 12, 15, 17, and 19 depend from claims 1, 11, or
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16. Because these claims are not separately argued with particularity, we are
not persuaded as previously stated.
The rejection for claims 1–6, 8, 11, 12, 15–17, and 19 is sustained.

OBVIOUSNESS REJECTION OVER SOENEN, DEVITO,
AND KIZER

Claims 13 and 20 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Soenen, DeVito, and Kizer. Ans. 9. Claims 13 and 20
depend directly from independent claims 11 and 16 respectively. Because
these claims are not separately argued with particularity, we are not
persuaded of error for this rejection as previously stated.
The rejection for claims 13 and 20 is sustained.

OBVIOUSNESS REJECTION OVER SOENEN, DEVITO,
AND COOKE

Claims 7, 9, 10, and 18 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Soenen, DeVito, and Cooke. Ans. 10. Claims 7, 9, 10,
and 18 depend from one of independent claims 1 and 16. Because these
claims are not separately argued with particularity, we are not persuaded of
error for this rejection as previously stated.
The rejection for claims 7, 9, 10, and 18 is sustained.

DECISION
The Examiner’s decision rejecting claims 1–13 and 15–20 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
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AFFIRMED

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