Ex Parte Bartling et al

Patent Trial and Appeal Board

Mar 26, 2018

13770304 (P.T.A.B. Mar. 26, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
131770,304 02/19/2013
23494 7590 03/28/2018
TEXAS INSTRUMENTS IN CORPORA TED
P 0 BOX 655474, MIS 3999
DALLAS, TX 75265
FIRST NAMED INVENTOR
Steven Craig Bartling
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-72884 3056
EXAMINER
SIMONETTI, NICHOLAS J
ART UNIT PAPER NUMBER
2137
NOTIFICATION DATE DELIVERY MODE
03/28/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte STEVEN CRAIG BARTLING and
SUDHANSHU KHANNA
Appeal2017-007846
Application 13/770,304
Technology Center 2100
Before BRUCE R. WINSOR, JEREMY J. CURCURI, and
AMBER L. HAGY, Administrative Patent Judges.
HAGY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from a rejection of
claims 1-3, 5, 7-12, and 16, which are all of the pending claims. 2 We have
jurisdiction under 35 U.S.C. § 6(b ).
We AFFIRM.
1 Appellants identify the real party in interest as Texas Instruments
Incorporated. (Br. 1.)
2 Claims 4, 6, 13-15, and 17 were canceled in an Amendment dated October
26, 2015. (See also Br. 8, 9, and 11 (Claims App'x).)
Appeal2017-007846
Application 13/770,304
STATEMENT OF THE CASE
Introduction
According to Appellants, "[t]his invention generally relates to
nonvolatile memory cells and their use in a system, and in particular, in
combination with logic arrays to provide nonvolatile logic modules." (Spec.
ii 2.)
Exemplary Claim
Claims 1 and 16 are independent. Claim 1, reproduced below, is
exemplary of the claimed subject matter and is the only independent claim
substantively argued on appeal:
1. A computing device apparatus providing non-volatile logic
based computing, the apparatus comprising:
a plurality of non-volatile logic element arrays;
a plurality of volatile storage element arrays;
at least one non-volatile logic controller configured to control the
plurality of non-volatile logic element arrays to store a machine state
represented by corresponding ones of the plurality of volatile
storage element arrays and to read out a stored machine state from
the plurality of non-volatile logic element arrays to the
corresponding ones of the plurality of volatile storage elements;
a multiplexer connected to variably connect individual ones of the
volatile storage element arrays to one or more corresponding
individual ones of the non-volatile logic element arrays.
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Application 13/770,304
References
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Y okozeki et al. ("Y okozeki")
Govindaraj et al. ("Govindaraj")
Bonella et al. ("Bonella")
Waldrip et al. ("Waldrip")
Dharmapurikar et al.
(''Dharmapurikar'')
Greene et al. ("Greene")
US 2004/0085846 Al
US 6,901,298 Bl
US 2007/0136523 Al
US 2008/0265962 Al
US 8,056,088 B 1
US 2014/0006887 Al
Rejections3
May 6, 2004
May 31, 2005
June 14, 2007
Oct. 30, 2008
Nov. 8, 2011
Jan.2,2014
Claim 7 stands rejected under 35 U.S.C. § 112, second paragraph, as
being indefinite. (Final Act. 2-3.)
Claims 1-3, 8, 10, and 12 stand rejected under 35 U.S.C. § 102(b) as
being anticipated by Bonella. (Final Act. 3---6.)
Claim 5 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Bonella and Waldrip. (Final Act. 6-8.)
Claim 7 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Bonella and Govindaraj. (Final Act. 8-9.)
Claim 9 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Bonella and Dharmapurikar. (Final Act. 9-11.)
Claim 11 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Bonella and Greene. (Final Act. 11.)
Claim 16 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Bonella, Yokozeki, Waldrip, Govindaraj, and
Dharmapurikar. (Final Act. 12-18.)
3 All rejections are under the provisions of 35 U.S.C. in effect prior to the
effective date of the Leahy-Smith America Invents Act of 2011.
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Application 13/770,304
Issue
The sole issue argued on appeal is whether the Examiner erred in
finding Bonella anticipates independent claim 1.
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments the Examiner has erred. We disagree with Appellants'
conclusions and we adopt as our own: (1) the findings and reasons set forth
by the Examiner in the action from which this appeal is taken (Final Act. 2-
21) and (2) the reasons set forth by the Examiner in the Examiner's Answer
in response to Appellants' Appeal Brief. (Ans. 2-5.) We concur with the
conclusions reached by the Examiner, and we highlight the following for
emphasis. 4
A. § 112 Rejection
The Examiner rejects claim 7 under 35 U.S.C. § 112, second
paragraph, for being indefinite. (Final Act. 2-3.) In particular, the
Examiner notes that claim 7 depends from claim 6, which has been canceled.
(Id. at 2; see also Br. 8 (Claims App'x).) The Examiner concludes "[t]here
is now insufficient antecedent basis" for the recitation in claim 7 of"[ t ]he
computing device apparatus of claim 6." (Id. at 2-3.)
Appellants do not address this rejection on appeal. Accordingly, we
summarily sustain this rejection. See Manual of Patent Examining
Procedure (MPEP) § 1205.02, 9th ed., Rev. 7, Nov. 2015 ("If a ground of
rejection stated by the examiner is not addressed in the appellant's brief,
4 Only those arguments made by Appellants have been considered in this
decision. Arguments Appellants did not make have not been considered and
are deemed to be waived. See 37 C.F.R. § 41.37(c)(l)(iv).
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Application 13/770,304
appellant has waived any challenge to that ground of rejection and the Board
may summarily sustain it.").
B. § 102 Rejection
In challenging the Examiner's rejection of independent claim 1 as
anticipated by Bonella, Appellants argue "Bonella does not teach at least one
non-volatile logic controller configured to control the plurality of non-
volatile logic element arrays to store a machine state represented by the
plurality of volatile storage elements." (Br. 5.) According to Appellants,
Bonella teaches "a controller that operates the volatile memory of the
memory module as a cache for the non-volatile memory of the memory
module." (Id.) In other words, Appellants argue the Examiner's
anticipation rejection is in error because, according to Appellants, Bonella
does not teach the non-volatile controller but instead discloses that the
controller manages volatile memory. (See also Ans. 2.)
We are not persuaded of error because Appellants' argument is
premised on an overly narrow reading of Bonella that ignores relevant
disclosure, as cited by the Examiner. In particular, the Examiner finds, and
we agree, "although [Bonella's] controller manages the volatile memory it
also is disclosed as managing the non-volatile memory as well." (Ans. 2
(emphasis added).) The Examiner reads Bonella's flash controller (Fig. 1)
as disclosing the claimed "non-volatile logic controller," and further finds
Bonella's "Memory Module Controller (MMC)," which is disclosed in
Figures 1 and 2 of Bonella, "includes the flash controller." (Id.) The
Examiner finds: "Bonella shows that the Flash Controller controls the
attached Flash Memories since all of the data which is read/written to the
Flash Memories must pass through the Flash Controller." (Id. at 3 (citing
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Appeal2017-007846
Application 13/770,304
Fig. 2 and i-fi-196, 101).) Thus, the Examiner finds, and we agree, "[although]
Appellant is correct that [Bonella's] MMC manages the volatile memory, it
also controls the non-volatile memory." (Id. at 2-3.)
The Examiner also finds the MMC, which includes the non-volatile
logic controller, is configured to control the non-volatile memory to store a
machine state from the volatile memory. (Final Act. 3--4; Ans. 2--4.) In
particular, the Examiner reads Bonella's disclosure of DRAM as
encompassing the claimed "volatile storage element arrays." (Final Act. 3.)
The Examiner then finds Bonella discloses scenarios in which the data in the
volatile DRAM is "flush[ ed]" to non-volatile FLASH, such as periodically
for backup or in the event of power loss. (Id. at 3--4; citing Bonella i-fi-169,
101.) As the Examiner notes in particular in the Answer:
For example, Bonella Paragraph 101: "Power loss algorithm--As
mentioned in connection with the DRAM flushing to FLASH,
the very likely scenario is a power loss event. An option for the
module is to have an uninterruptible power supply with energy
reserves to Flush the critical DRAM data to the Flash on the
memory module .... When the memory module controller detects
a power loss event, the data that is flagged as critical is flushed
to the FLASH." ...
(Ans. 3 (quoting Bonella i-f 101) (emphasis added).)
As noted above, we agree the Examiner's findings are supported by
the disclosure of the cited reference. Appellants' arguments, which do not
address these findings and otherwise ignore relevant disclosure of Bonella,
do not persuade us of Examiner error. We also note Appellants' statement
that "Bonella teaches away from" the claimed invention is not only devoid
of reasoning, it is also legally inapposite to an anticipation analysis. As our
reviewing court has explained, "A reference is no less anticipatory if, after
disclosing the invention, the reference then disparages it .... [T]he question
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Application 13/770,304
whether a reference 'teaches away' from the invention is inapplicable to an
anticipation analysis." Celeritas Techs., Ltd. v. Rockwell Int'! Corp., 150
F.3d 1354, 1361 (Fed. Cir. 1998).
Appellants' additional argument as to the Examiner's rejection of
independent claim 1 (and the additional claims argued together with claim 1)
amounts to no more than the terse statement that Bonella does not teach the
recited limitation of a "multiplexer variably connected [sic] to individual
ones of the volatile storage element arrays to one or more corresponding
individual ones of the non-volatile local element arrays." (Br. 5.) Such
conclusory attorney assertions have little or no value in identifying the
Examiner's alleged error, and, consequently, have little persuasive value.
See 3 7 C.F .R. § 41.3 7 ( c )(iv) ("A statement which merely points out what a
claim recites will not be considered an argument for separate patentability of
the claim."); see also In re Lovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011).
Moreover, the Examiner finds, and we agree, Bonella discloses "data, i.e. the
critical DRAM data, passing between the DRAM and Flash memories flows
through the multiplexers within the Router of the MMC," as shown in Figure
2 of Bonella in which the "DRDat" and "FLDat" data bus lines run between
the Router and the respective DRAM and Flash Controllers, and also
"DATA" bus lines run between the DRAM and Flash Controllers and their
respective memory interfaces. (Ans. 5 (citing Bonella i-f 43 and Fig. 2)
(emphasis added).) Appellants do not address these findings by the
Examiner, which we agree are supported by the cited disclosures.
For the foregoing reasons, we are not persuaded of error in the
Examiner's rejection of independent claim 1under35 U.S.C. § 102(b) as
anticipated by Bonella, and we, therefore, sustain that rejection, along with
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the rejection of dependent claims 2, 3, 8, 10, 12, which are rejected on the
same basis and not separately argued. (Br. 6.)
C. § 103 Rejections
Appellants have not presented separate, substantive, persuasive
arguments with respect to claims 5, 7, 9, 11, or 16, which are rejected under
35 U.S.C. § 103(a) as being unpatentable over the combination of Bonella
with one or more references. (See Final Act. 6-18.) As to dependent claims
5, 7, 9, and 11, Appellants assert these claims "stand or fall together with
independent claim 1." (Br. 6.) As to independent claim 16, Appellants
assert "claim 16 is distinguishable over cited references for at least the same
reasons as claim 1." (Id.) Without independent arguments, however, such
contentions fail to constitute a separate issue of patentability. We, therefore,
are not persuaded the Examiner erred in rejecting these claims. See In re
Lovin, 652 F.3d 1349, 1356 (Fed. Cir. 2011) ("We conclude that the Board
has reasonably interpreted Rule 41.37 to require applicants to articulate more
substantive arguments if they wish for individual claims to be treated
separately."). Accordingly, we sustain the Examiner's rejection of these
claims under 35 U.S.C. § 103(a). See 37 C.F.R. § 41.37(c)(l)(iv).
DECISION
For the above reasons, the Examiner's rejections of claims 1-3, 5, 7-
12, and 16 are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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