Ex Parte Barrett et al

Board of Patent Appeals and Interferences

Mar 28, 2012

11008813 (B.P.A.I. Mar. 28, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/008,813 12/09/2004 Wayne M. Barrett ROC920040283US1 1647
7590 03/28/2012
Robert Williams
IBM Corporation
Intellectual Property Law Dept. 917
3605 Hwy. 52 North
Rochester, MN 55901
EXAMINER
SPITTLE, MATTHEW D
ART UNIT PAPER NUMBER
2111
MAIL DATE DELIVERY MODE
03/28/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte WAYNE M. BARRETT and BRIAN T. VANDERPOOL
____________________

Appeal 2010-000193
Application 11/008,8131
Technology Center 2100
____________________

Before DEBRA K. STEPHENS, JAMES R. HUGHES, and
ANDREW J. DILLON, Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellants appeal from the Examiner’s rejection of claims 1-20.
Claim 21 has been canceled. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 Application filed December 9, 2004. The real party in interest is
International Business Machines Corp. (Br. 2.)
Appeal 2010-000193
Application 11/008,813

2

Appellants’ Invention
The invention at issue on appeal concerns an apparatus and method
for processing commands on a bus by a memory controller. (Spec. 1:10 to
2:9; Abstract.)2
Representative Claim
Independent claim 1, reproduced below with the key disputed
limitations emphasized, further illustrates the invention:
1. A method of processing commands on a bus,
comprising:
in a first phase of bus command processing, receiving a
new command from a processor in a memory controller via the
bus, wherein a command on the bus is processed in a plurality
of sequential phases;
determining whether the new command requires access
to a memory address that is to be accessed by any pending
commands stored in the memory controller;
starting to perform memory controller tasks the results of
which are required by a second phase of bus command
processing;
before performing the second phase of bus command
processing on the new command, determining whether there are
any pending commands previously received that require access
to a same memory location as the new command in the memory
controller that should complete before the second phase of
processing is performed on the new command; and
if there are no pending commands previously received in
the memory controller that should complete before the second
phase of processing is performed on the new command,

2 We refer to Appellants’ Specification (“Spec.”) and Appeal Brief (“App.
Br.”) filed April 17, 2009. We also refer to the Examiner’s Answer (“Ans.”)
mailed June 19, 2009.
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Application 11/008,813

3

performing the second phase of processing on the new
command without requiring the memory controller to insert a
processing delay on the bus.

Rejection on Appeal
The Examiner rejects claims 1-20 under 35 U.S.C. § 102(b) as being
anticipated by U.S. Patent No. 6,425,043 B1 issued Jul. 23, 2002
(“Jeddeloh”).

ISSUE
Based on our review of the administrative record, Appellants’
contentions, and the Examiner’s findings and conclusions, the pivotal issue
before us is as follows:
Does the Examiner err in finding that Jeddeloh discloses:
before performing the second phase of bus command
processing on the new command, determining whether there are
any pending commands previously received that require access
to a same memory location as the new command in the memory
controller that should complete before the second phase of
processing is performed on the new command
within the meaning of claim 1 and commensurate claim 11?

FINDINGS OF FACT
We adopt the Examiner’s findings in the Answer and Final Office
Action as our own, except as to those findings that we expressly overturn or
set aside in the Analysis that follows.

Appeal 2010-000193
Application 11/008,813

4

ANALYSIS
Appellants argue independent claim 1 together with independent
claim 11 and dependent claims 2-10 and 12-20 as a group based on claim 1.
(Br. 10-14.) Therefore, we select claim 1 as representative of Appellants’
arguments and groupings. 37 C.F.R. § 41.37(c)(1)(vii). See In re Nielson,
816 F.2d 1567, 1572 (Fed. Cir. 1987). We consider only those arguments
that Appellants have actually raised in their Brief. Arguments that
Appellants could have made but chose not to make in the Brief have not
been considered and are deemed to be waived. See 37 C.F.R.
§ 41.37(c)(1)(vii).
Appellants have the opportunity on appeal to the BPAI to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006) (citing In re Rouffet, 149 F.3d 1350, 1355 (Fed. Cir. 1998)).
The Examiner sets forth a detailed explanation of the anticipation rejections
in the Examiner’s Answer with respect to each of the claims (Ans. 3-15)
and, in particular, claim 1 (id. at 3-4, 13-15). Therefore, we look to the
Appellants’ Brief to show error in the proffered findings and conclusions.
See Kahn, 441 F.3d at 985-86.
Claim 1
The Examiner rejects Appellants’ independent claim 1 as being
anticipated by Jeddeloh. (Ans. 3-4, 13-15.) Specifically, the Examiner
submits that Jeddeloh describes sequential multiple phases of bus command
processing in a memory controller, including determining whether a new
command accesses the same memory location/address (bank) as any
previously received pending commands. (Ans. 3-4; 13-14 (citing col. 4, ll.
22-37; col. 5, ll. 8-14).)
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Appellants contend that the claim requires two separate
determinations as to the new command and the memory location (Br. 12-13),
“Jeddeloh fails to disclose the second determination of whether there are any
pending commands previously received that require access that should
complete before the second phase of processing is performed on the new
command” (Br. 12), and Jeddeloh does not disclose “identifying ‘any
pending commands . . . that should complete before the second [phase] of
processing is performed on the new command’” (Br. 13).
Upon consideration of the evidence on this record and each of
Appellants’ contentions, we find that the preponderance of evidence on this
record supports the Examiner’s finding that the subject matter of Appellants’
claim 1 is anticipated by Jeddeloh. Accordingly, we sustain the Examiner’s
rejection of claim 1 for the reasons set forth in the Answer, which we
incorporate herein by reference. (Ans. 3-4, 13-15.)
As explained by the Examiner, Jeddeloh describes the claimed
functionality (Ans. 13-14; see Jeddeloh, Fig. 4) and Appellants’ claim does
not preclude adding delays (stalls) to processing (Ans. 15). In the case
where the new command and a pending command access the same memory
resource, a processing delay is added to the bus, and the functionality is
identical to Jeddeloh. (See Fig. 4; Spec. 4:24 to 5:6, 8:23 to 11:32 (step
408).) The language “that should complete before the second phase of
processing is performed on the new command” (claim 1) does not further
limit the claim either structurally or functionally. We agree with the
Examiner that Jeddeloh discloses each feature of Appellants’ claim.
Thus, we find Appellants’ contrary arguments unpersuasive of error in
the Examiner’s rejection for the reasons explained above. Further, we note
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that Appellants failed to file a Reply Brief to rebut the findings and
responsive arguments made by the Examiner in the Answer. It follows that
Appellants do not persuade us of error in the Examiner’s anticipation
rejection of representative claim 1. Appellants also do not persuade us of
error in the Examiner’s anticipation rejection of independent claim 11 and
dependent claims 2-10 and 12-20 not separately argued with particularity
(supra). Accordingly, we affirm the Examiner’s anticipation rejection of
claims 1-20.

CONCLUSION OF LAW
Appellants have not shown that the Examiner erred in rejecting claims
1-20 under 35 U.S.C. § 102(b).

DECISION
We affirm the Examiner’s rejection of claims 1-20 under 35 U.S.C.
§ 102(b).

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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