Ex Parte Ang et al

Board of Patent Appeals and Interferences

Jan 26, 2012

11624095 (B.P.A.I. Jan. 26, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte LIN PING ANG and STEVEN HUANG
____________

Appeal 2010-000250
Application 11/624,095
Technology Center 2800
____________

Before HOWARD B. BLANKENSHIP, THU A. DANG, and
ANDREW J. DILLON, Administrative Patent Judges.

DILLON, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-10 and 13-22. Claims 11 and 12 are allowed. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.

STATEMENT OF THE CASE
Appellants’ invention is directed to an integrated circuit which
includes a number of individually powered elements. A mesh is provided
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between individually powered elements to provide power and/or ground and
the mesh may be on different levels, such that one portion of the mesh lies
exactly over another portion. See Abstract.
Claim 1 is illustrative, with key disputed limitations emphasized:
1. An integrated circuit chip comprising:
a plurality of power consuming elements, each said
power consuming element operating to obtain independent data,
said power consuming elements, located in an array at different
areas covering a surface of the chip; and
a power grid, having a first power connecting portion,
which is adapted to be attached to a source of power, and
having a first plurality of parallel elements, and a second
plurality of parallel elements, which extend substantially
orthogonal to said first plurality of elements and are connected
to said first plurality of parallel elements, and said power grid
extends across an area defined by said plurality of power
consuming elements, said chip having multiple different levels,
each level having connection parts thereon, and wherein both
said power consuming elements, and said power grid are on the
same level of the chip.

The Examiner relies on the following as evidence of unpatentability:
Lee US 5,331,179 July 19, 1994
Theil US 6,396,118 B1 May 28, 2002
Iwanczyk US 2002/0148967 A1 Oct. 17, 2002

THE REJECTIONS
1. The Examiner rejected claims 1-4 and 7-10 under 35 U.S.C.
§ 102(b) as anticipated by Lee. Ans. 3-5.1

1 Throughout this opinion, we refer to the Appeal Brief filed February 25,
2009 (as supplemented Apr. 27, 2009) and the Examiner’s Answer mailed
June 22, 2009.
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2. The Examiner rejected claims 20-22 under 35 U.S.C. § 102(b)
as anticipated by Theil. Ans. 5-6.
3. The Examiner rejected claims 5, 6, and 14-19 under 35 U.S.C.
§ 103(a) as unpatentable over Lee and Iwanczyk. Ans. 6-9.
4. The Examiner rejected claim 13 under 35 U.S.C. § 103(a) as
unpatentable over Lee and Theil. Ans. 9-10.

CONTENTIONS
Regarding claim 1, the Examiner finds that Lee discloses an
integrated circuit having a plurality of power consuming elements in an
array and a power grid having a first plurality of elements which are
orthogonal to, and connected to a second plurality of elements, and which
extends across the array of power consuming elements. Ans. 3-5.
With regard to claim 20, the Examiner finds that Theil discloses an
image sensor chip having an array of individual elements which each receive
separate data, a chip power connection, and a mesh of power delivering
lines. Ans. 5-6.
Regarding claim 5, the Examiner finds that Lee discloses an
integrated circuit having a plurality of power consuming elements in an
array and a power grid having a first plurality of elements which are
orthogonal to, and connected to a second plurality of elements, and which
extends across the array of power consuming elements. The Examiner
acknowledges that Lee does not teach that the power grid surrounds groups
of power consuming elements, but cites Iwanczky for disclosing a silicon
detector array including a grid which surrounds groups of four detectors.
Ans. 6-9.
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With regard to claim 1, Appellants argue that Lee discloses address
and sense lines and if the address and sense lines of Lee were “connected
together” it would defeat the purpose of having separate lines. Br. 10.
Regarding claim 20, Appellants argue that requiring that the power
delivering lines “extend against at least one side of each of said individual
elements” requires the power delivering lines to be on the same level as the
elements. Br. 12-13.
With regard to claim 5, Appellants argue that the cited references fail
to suggest a power grid that “surrounds groups of power consuming
elements.” Br. 13.
The issues before us, then, are as follows:

ISSUES
1. Under § 102, has the Examiner erred in rejecting claims 1-4 and 7-
10 by finding that Lee anticipates an integrated circuit having a plurality of
power consuming elements in an array and a power grid having a first
plurality of elements which are orthogonal to, and connected to a second
plurality of elements, and which extends across the array of power
consuming elements?
2. Under § 102, has the Examiner erred in rejecting claims 20-22 by
finding that Theil anticipates an image sensor chip having an array of
individual elements which each receive separate data, a chip power
connection and a mesh of power delivering lines?
3. Under § 103, has the Examiner erred in rejecting claims 5, 6, and
14-19 by finding that Lee and Iwanczyk, collectively, suggest an integrated
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circuit having a plurality of power consuming elements in an array and a
power grid having a first plurality of elements which are orthogonal to, and
connected to a second plurality of elements, and which extends across the
array of power consuming elements wherein the power grid surrounds
groups of detectors?

FINDINGS OF FACT (FF)
We find that the following enumerated findings of fact are supported
by at least a preponderance of the evidence. Ethicon, Inc. v. Quigg, 849
F.2d 1422, 1427 (Fed. Cir. 1988) (explaining the general evidentiary
standard for proceedings before the Office).
1. Lee discloses an array of microplates 4a-4n within a grid
formed by a plurality of parallel address lines X1-Xn and a plurality of
parallel sense lines Y1-Yn, wherein the plurality of sense lines are
orthogonal to the address lines. Each address line is connected to a sense
line via a transistor 5. Lee, col. 6, ll. 6-65 (describing Figure 2).
2. Lee discloses the array of microplates is surrounded by an
electrically conductive grid 13, which underlies and runs substantially along
the directions of the address and sense lines. Lee, col. 7, ll. 3-27 (describing
Figure 3).
3. Theil discloses an image sensor chip having an array of
individual photo sensors which each receive separate data wherein a
conductive mesh of power lines is “electrically and physically connected to
the photo sensors.” Theil, col. 2, ll. 55-60.
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4. Iwanczyk discloses a silicon detector array having a power
supply grid 52 which surrounds a plurality of pixels. Iwanczyk, ¶[0061]
(describing Figure 4).

ANALYSIS
Rejections Under §102
Appellants traverse the Examiner’s citation of Lee with respect to the
rejection of claims 1 and 7 under §102, arguing that the Examiner has failed
to provide a prima facie showing of unpatentability. The basis for
Appellants’ arguments is a belief that a connection between the address lines
and sense lines of Lee would defeat the purpose of having separate address
and sense lines. Br. 10.
We agree with Appellants, if the address and sense lines of Lee were
directly connected it would indeed defeat the purpose of having separate
address and sense lines; however, we find that the address and sense lines of
Lee are indeed connected, via transistor 5 (FF1).
“[D]uring examination proceedings, claims are given their broadest
reasonable interpretation consistent with the specification.” In re Hyatt, 211
F.3d 1367, 1372 (Fed. Cir. 2000) (citations omitted). We hold that the
broadest reasonable interpretation of “connected to” encompasses a
connection through an intermediate element, such as transistor 5, as shown
within Figure 2 of Lee. This is especially true in light of Appellants’ ability
to amend their claim language during prosecution to recite “directly
connected” or to, in some other manner, distinguish their claims from the
cited art.
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Appellants separately argue the patentability of claim 8, noting a
belief that Lee fails to disclose two separate meshes on separate levels, as set
forth in their claim. We find that Lee discloses a mesh 13, which underlies
the address and sense lines. (FF2).
Consequently, we find Appellants’ arguments unavailing and we are
not persuaded that the Examiner erred in rejecting claims 1, 7, and 8 as
anticipated by Lee. We also find that the Examiner did not err in rejecting
claims 2-4 and 9-10, which were not separately argued, as anticipated by
Lee.
Appellants argue that the Examiner’s rejection of claims 20-22 as
anticipated by Theil under §102 is improper, noting that claim 20 recites that
the power delivering lines “extend against at least one side of each of said
individual elements”. Br. 12. Appellants argue that Theil discloses that the
apertures within the mesh serve to funnel light towards the pixel electrodes
and consequently the mesh cannot be on the same level as the pixel
electrodes. Br. 13.
We find Appellants’ arguments are not commensurate with the scope
of claim 20. Claim 20 does not recite that the mesh and elements are on the
same level within the integrated circuit. Further, Theil expressly recites that
the conductive web therein is “electrically and physically connected to the
photo sensors.” (FF3).
Therefore, we find that the Examiner did not err in rejecting claim 20,
and claims 21 and 22 not separately argued, as anticipated under §102 by
Theil.
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Rejections Under §103
Appellants argue that the Examiner’s rejection of claims 5, 6, and 14-
19 under §103 as unpatentable over Lee and Iwanczyk is not well founded,
noting that claim 5 recites the connection which exists between the
orthogonal power grid structures, and the fact that the power grid elements
surround groups of photoreceptors, not each photoreceptor individually. Br.
13.
As found by the Examiner, and as we find above with respect to claim
1, Lee discloses a connection between address and sense lines through
transistor 5, which we find to be within the broadest reasonable
interpretation of Appellants’ claims.
Appellants argue that the implant regions surrounding the groups of
detector arrays within Iwanczyk, which the Examiner equates with the
power grid elements, are not a power grid, but are merely for
“semiconductor doping, and to improve the light sensitivity of the arrays.”
Br. 13.
We find that Iwanczyk discloses a grid 52, formed by an implant
region, which supplies a voltage V1 to a group of pixels. Consequently we
find that grid 52 is indeed a power grid. (FF4).
Appellants argue that claim 14 distinguishes from the Examiner’s
cited art by virtue of the claimed limitation of the photoreceptor elements
and the power grid on the same level within the chip.
For the reasons we set forth above with respect to claim 1, we find
that the address and sense lines of Lee are set forth on the same level as the
microplates of Lee.
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We are therefore not persuaded that the Examiner erred in rejecting
claim 5 and 14, and claims 6 and 15-19 not separately argued with
particularity under §103.
Finally, the Examiner has rejected claim 13 as unpatentable under
§ 103 over Lee and Theil. Appellants have not argued the patentability of
claim 13 separately with particularity and consequently those arguments are
considered waived. See 37 C.F.R. § 41.37(c)(1)(vii).

CONCLUSION
The Examiner did not err in rejecting claims 1-4, 7-10, and 20-22
under § 102, and claims 5, 6, and 13-19 under § 103.

ORDER
The Examiner’s decision rejecting claims 1-10 and 13-22 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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