Ex Parte Almasi et al

Patent Trial and Appeal Board

Mar 27, 2018

13917240 (P.T.A.B. Mar. 27, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/917,240 06/13/2013 Gheorghe Almasi
73109 7590 03/29/2018
Cuenot, Forsythe & Kim, LLC
20283 State Road 7
Ste. 300
Boca Raton, FL 33498
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
CA920130038US1_8150-0388 5903
EXAMINER
VILLANUEVA, LEANDRO R
ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
03/29/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ibmptomail@iplawpro.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GHEORGHE ALMASI, BARNABY DALTON,
ILIE G. TANASE, and ETTORE TIOTTO
Appeal2017-008138
Application 13/917 ,240
Technology Center 2100
Before MAHSHID D. SAADAT, JOHN D. HAMANN, and
JASON M. REPKO, Administrative Patent Judges.
REPKO, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1-14. App. Br. 1.2 We have jurisdiction under 35 U.S.C.
§ 6(b ). We reverse.
1 Appellants identify the real party in interest as IBM Corporation.
App. Br. 1.
2 Throughout this opinion, we refer to the Final Rejection ("Final Act.")
mailed October 6, 2016; the Appeal Brief ("App. Br.") filed December 21,
2016; the Examiner's Answer ("Ans.") mailed March 10, 2017; and the
Reply Brief ("Reply Br.") filed May 9, 2017.
Appeal2017-008138
Application 13/917 ,240
THE INVENTION
Appellants' invention manages a symmetric heap and allocates
distributed data structures. Spec. i-f 8. The invention relates to a
system with multiple processes distributed across networked
computers. Id. i-f 2. A partition is the independent virtual-memory
address space for each distributed process. Id. The collection of all
such partitions for a program is called the Partitioned Global Address
Space (PGAS). Id. A PGAS program distributes data structures
across all partitions. Id. i-f 5. This allows each process to work on
local data. Id. The system tracks the data structure's location using a
table or shared variable directory (SVD), which maps handles to data
structures. Id. i-fi-1 6, 7. In this approach, a target process must
translate from a handle to a virtual base address. Id. i-f 7. This
translation, however, reduces performance. Id.
To avoid interrupting the target process with translations,
remote direct-memory access (RDMA) can be used for read and write
operations. Id. To use RDMA, the requesting process must know the
data structure's virtual memory address in the target process. Id. But
in PGAS with SVD, the requesting process does not know this
address. Id. Consequently, RDMA cannot be used to accelerate these
read and write operations. Id.
To overcome this limitation, the invention defines a symmetric
heap to include a symmetric partition for each process of a PGAS.
Id. i-f 9. Each symmetric partition has the same starting virtual
memory address. Id. An allocator process then maintains isomorphic
fragmentation among these symmetric partitions. Id. i-f 86.
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Application 13/917 ,240
Isomorphism means that the data structure in each partition has the
same virtual-memory address in each partition. Id. Because of this
property, each process can access data from the data structure in target
process's symmetric partition using RDMA. Id. i-f 67. In this way, the
system exploits the speed of RDMA while maintaining the benefits of
SVD. Id. i-f 87.
Claim 1 is reproduced below with our emphasis:
1. A system comprising:
a processor programmed to initiate executable operations
compnsmg:
defining a symmetric heap comprising a symmetric
partition for each process of a partitioned global address space
(PGAS) system;
wherein each symmetric partition of the symmetric heap
begins at a same starting virtual memory address and has a same
global symmetric break;
configuring one process of a plurality of processes of the
PGAS system as an allocator process that controls allocation of
blocks of memory for each symmetric partition of the symmetric
heap; and
maintaining, by the allocator process, isomorphic
fragmentation among the symmetric partitions of the symmetric
heap.
THE EVIDENCE
The Examiner relies on the following as evidence:
Archambault et al.
Frank
Elliott et al.
US 2005/0149903 Al
US 2010/0299495 Al
US 2013/0177017 Al
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July 7, 2005
Nov. 25, 2010
July 11, 2013
Appeal2017-008138
Application 13/917 ,240
THE REJECTIONS
Claims 1-14 stand provisionally rejected on the ground of
nonstatutory double patenting as being unpatentable over claims 1-7 of
copending Application No. 13/917,906. Final Act. 3-13.
Claims 1, 2, 4, 5, 8, 9, 11, and 12 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over Archambault and Elliott. Final Act. 13-18.
Claims 3, 6, 7, 10, 13, and 14 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over Archambault, Elliott, and Frank. Final Act. 18-21.
THE PROVISIONAL DOUBLE-PATENTING REJECTION
Although Appellants do not provide arguments against this rejection
(see App. Br. 3 n. 1), we decline to reach the Examiner's provisional
rejection of claims 1-14 on the ground of non-statutory obviousness-type
double patenting. See Ex parte Moncla, 95 USPQ2d 1884, 1885 (BP AI
2010) (precedential) (explaining that panels may decline to reach provisional
obviousness-type double patenting rejections).
THE OBVIOUSNESS REJECTION OVER ARCHAMBAULT AND
ELLIOTT
The Examiner's Findings
The Examiner finds that Archambault teaches every limitation recited
in independent claim 1 except for the symmetric partition and maintaining
isomorphic fragmentation. Final Act. 14--15. In concluding that claim 1
would have been obvious, the Examiner cites Elliott as teaching this feature.
Id. at 15. According to the Examiner, Archambault uses one thread to
control the block allocation for each partition. Id. at 14 (citing
Archambault i-fi-18, 9, Fig. 1 ).
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Application 13/917 ,240
Appellants ' Contentions
Appellants argue that Archambault does not use one process to control
block allocations for each of the plurality of partitions. App. Br. 12-16;
Reply Br. 5. According to Appellants, Archambault teaches each process
performs allocation for its own partition. App. Br. 15-16 (citing
Archambault i-fi-122, 26); Reply Br. 5.
Issue
Under§ 103, has the Examiner erred in rejecting independent claim 1
by finding that Archambault would have taught or suggested one process to
control block allocations for each of the plurality of partitions?
Analysis
Claim 1 recites, in part, "a symmetric partition for each process" and
"configuring one process of a plurality of processes of the PGAS system as
an allocator process that controls allocation of blocks of memory for each
symmetric partition of the symmetric heap." That is, claim 1 requires that
one process controls block allocation for each partition for each of the
heap's processes.
For example, the Specification describes that one process can allocate
memory for all processes. Spec. i178. In this embodiment, the other
processes do not know whether a distributed data structure is in their
partition unless the requesting process notifies other processes. Id. These
other processes also cannot allocate to an allocator-marked memory block.
Id. In this way, the allocator processor controls allocation and maintains
isomorphism in the partitions. Id. Although this embodiment is illustrative,
it nevertheless informs our understanding of the limitation at issue.
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Application 13/917 ,240
The Examiner finds that Archambault teaches one process to control
block allocations for each of a plurality of partitions. Final Act. 14 (citing
Archambault i-f 8, Fig. 1 ). We agree with Appellants that the Examiner erred
in this regard. See App. Br. 12-16.
In particular, Archambault teaches a shared-memory machine with a
directory of shared variables. Archambault i-fi-1 8, 17, cited in Final Act. 14.
The directory of shared variables is a partitioned data structure stored in
shared memory. Archambault i-fi-117, 19. Each thread uses a mutually
exclusive partition. Id. i-f 18. Each partition is an independent, resizable
array of pointers. Id. That is, if one thread declares a large number of
shared variables, only that thread's partitions will grow. Id.
Unlike the recited allocator process, Archambault's threads do not
control block allocations for each of the plurality of partitions. Id. i-f 22.
Rather, Archambault explains that the calling thread allocates space its own
partition. Id.; see also id. i-f 26.
The Examiner also cites to Archambault's distributed memory
embodiment. Final Act. 14 (citing Archambault i-f 9). To be sure, the calling
thread shares some information with other threads in this embodiment. See
Archambault i-f 9. But, in distributed-memory machines, each thread stores a
directory of shared memory in its private memory. Id. Archambault
explains that only the owning thread can access private memory. Id. i-f 6,
cited in Final Act. 14. And like Archambault's shared-memory
embodiment, the calling thread also allocates space in its own partition in the
distributed-memory embodiment. Archambault i-f 22.
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Application 13/917 ,240
On this record, we are persuaded by Appellants' argument that
Archambault lacks one process to control block allocations for each of a
plurality of partitions. See App. Br. 15-16 (citing Archambault i-fi-122, 26).
Accordingly, we do not sustain the Examiner's rejection of
independent claim 1, independent claim 8, which recites similar limitations, 3
and claims 2, 4, 5, 9, 11, and 12, which depend from claims 1 and 8.
THE REJECTION OVER ARCHAMBAULT, ELLIOTT, AND FRANK
For the same reasons discussed above in connection with claim 1, we
do not sustain the Examiner's rejections of dependent claims 3, 6, 7, 10, 13,
and 14. The Examiner does not rely upon Frank to teach the limitation
missing from Archambault and Elliott, and, thus, Frank does not cure the
deficiency discussed above. See Final Act. 18-21.
3 Claim 8 recites similar limitations to claim 1 in a computer program
product comprising "a computer readable storage medium." Our precedent
indicates that the term "storage" does not exclude patent-ineligible transitory
signals per se from the claim's scope when the Specification is silent. See
Ex parte Mewherter, 107 USPQ2d 1857, 1859---60 (PTAB 2013)
(precedential). Here, the Specification is not silent. See, e.g., Spec. i-fi-121-
22 (discussing mediums and signals). It is well-established that during
examination, claims are given their broadest reasonable interpretation
consistent with the Specification. See In re Montgomery, 677 F.3d 1375,
1379 (Fed. Cir. 2012). We leave to the Examiner to determine whether the
interpretation that the recited storage medium encompasses transitory signals
per se is consistent with the Specification and to decide whether to reject the
claims, to clarify that the claims are eligible, or to take other action. See
MPEP § 2106.07(c) (9th ed., Rev. 08.2017, Jan. 2018) ("When the claims
are deemed patent eligible, the examiner may make clarifying remarks on
the record.").
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Application 13/917 ,240
DECISION
We reverse the Examiner's rejection of claims 1-14.
REVERSED
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