Ex Parte Akkar et al

Patent Trial and Appeal Board

Jul 31, 2014

11531043 (P.T.A.B. Jul. 31, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MEHDI-LAURENT AKKAR, AYMERIC STEPHANE VIAL,
and OLIVIER CHARLES SCHUEPBACH
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Appeal 2012-001347
Application 11/531,043
Technology Center 2100
____________

Before JOSEPH L. DIXON, JAMES R. HUGHES, and ERIC S. FRAHM,
Administrative Patent Judges.

FRAHM, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1, 3–8, 16, and 18–22. App. Br. 2. Claims 2, 9–15, and
17 are canceled. Id. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

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REJECTIONS
The Examiner rejected claims 1, 3, and 4 under 35 U.S.C. § 102(e) as
anticipated by U.S. Patent Application Pub. No. 2005/0216651 A1 to
Tanabiki. Ans. 4–6.
The Examiner rejected claims 5–7 under 35 U.S.C. § 103(a) as
unpatentable over Tanabiki and U.S. Patent No. 7,484,074 B2 to Hepkin. Id.
at 7–8.
The Examiner rejected claim 8 under § 103(a) as unpatentable over
Tanabiki and U.S. Patent No. 5,734,822 to Houha. Id. at 8.
The Examiner rejected claims 16 and 9–22 under § 103(a) as
unpatentable over Tanabiki and U.S. Patent No. 6,272,587 B1 to Irons. Id.
at 9–11.
ILLUSTRATIVE CLAIM
Illustrative claim 1 is reproduced below (with paragraphing added).
1. A system, comprising:
a processor;
a random access memory (RAM) coupled to the processor, the
RAM divided into public RAM and secure RAM;
a system memory coupled to the processor, wherein the system
memory stores RAM resize instructions that, when executed,
enable the public RAM and the secure RAM to be dynamically
resized; and
a cryptographic hardware accelerator (HWA),
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wherein the system memory stores save/restore secure RAM
instructions that, when executed, perform a save operation that
saves all secure RAM content to non-volatile memory and a
restore operation that restores all secure RAM content from the
non-volatile memory, and
wherein the system memory stores HWA arbitration
instructions that, when executed, enable the cryptographic
HWA to operate in a secure mode and a public mode.
ANALYSIS
Claims 1 and 16 are independent. All remaining claims depend from
one of claims 1 and 16 and, accordingly, incorporate their respective
limitations. We reverse all rejections in view of the following two Examiner
errors as to claims 1 and 16.
First Error
Claim 1 requires a “cryptographic HWA” and “HWA arbitration
instructions that, when executed, enable the cryptographic HWA to operate
in a secure mode and a public mode.” Claim 16 requires a “cryptographic
HWA” and “HWA arbitration instructions that, when executed, enable the
cryptographic HWA to be shared by a secure application and a public
application.” In all rejections, the Examiner finds that Tanabiki’s system
operates in accord with the HWA arbitration instructions as claimed. See
Ans. 6 (claim 1) and 9 (claim 16); see also id. at 7, 8, and 10 (respective
applications of Hepkin, Houha, and Irons). Acknowledging that Tanabiki
does not ipsissimis verbis describe a “hardware accelerator,” the Examiner
addresses the “hardware accelerator” terminology of claim 1 as follows:
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[A]s far as the scope and merit of claim 1 are concerned, any
functional unit(s) that “perform a save operation that saves all
secure RAM content to non-volatile memory and a restore
operation that restores all secure RAM content from the
nonvolatile memory” would qualify as a “hardware
accelerator.”
Ans. 17. The Examiner presents the same determination for the “hardware
accelerator” terminology of claim 16. Id. at 27.
Appellants reply:
Examiner thus determines: “a cryptographic hardware
accelerator = any functional unit” so long as its function is “to
perform a save operation that saves all secure RAM content to
nonvolatile memory and a restore operation that restores all
secure RAM content from the non-volatile memory”. Such
determination is without factual support and ignores the plain
and ordinary meaning of the words “hardware accelerator”
. . . [.]
One having ordinary skill in the art would recognize that
a hardware accelerator in its most basic sense is a device that
speeds up processing or transmission (see: Computer Desktop
Encyclopedia ATTACHMENT-A, p. 1 & 2; PCMAG.COM
Encyclopedia ATTACHMENT-B, p. 1; Free Online Dictionary
ATTACHMENT-C, p. 1; Webster’s Online Dictionary
ATTACHMENT-D, p. 4). In addition to the above broader
definition, Webster’s Online Dictionary also sets forth a more
narrow definition: “Additional hardware to perform some
function faster than is possible in software running on the
normal CPU” (p. 1). . . .
Reply Br. 3-4 (emphases omitted).
Appellants’ extrinsic evidence for definitions of “hardware
accelerator” (attachments A–D) is of minor utility to construing a meaning
in the present context, for at least two reasons. First, the cited references are
not “contemporaneous” publications; that is, are not persuasive evidence for
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the meaning of “hardware accelerator” at the time of the present
application’s effective filing date. See e.g., Brookhill-Wilk 1, LLC. v.
Intuitive Surgical, Inc., 334 F.3d 1294, 1299 (Fed. Cir. 2003) (explaining the
importance of considering “contemporaneous” definitions). Second,
Appellants have not shown the cited definitions to be consistent with the
Specification’s usages of “hardware accelerator.” Id. at 1300 (“[I]ntrinsic
record must always be consulted to identify which of the different possible
dictionary meanings is most consistent with the use of the words by the
inventor.”).
However, Appellants’ extrinsic evidence nonetheless demonstrates
that “hardware accelerator” has a recognized meaning within the art. And,
our sua sponte search for contemporaneous meanings also demonstrates that
“hardware accelerator” has a recognized meaning within the art.1 See
Phillips v. AWH Corp., 415 F.3d 1303, 1316–17 (Fed. Cir. 2005) (en banc)
(upholding a district court’s sua sponte consideration of extrinsic evidence
for a claim term meaning).
We therefore find that “hardware accelerator” does not serve claims 1
and 16 as a mere arbitrary label of “any functional unit(s),” as contended by
the Examiner (see supra 3, Examiner block quote (quoting Ans. 17)). In
other words, “hardware accelerator” does not merely reflect a corresponding
functional unit’s performance of the claimed inventions’ HWA functions;

1 A search for contemporaneous U.S. patents – namely within one year
before and after the present application’s filing date – with abstracts
referencing “hardware accelerator” yielded 24 patents. See e.g.,
http://patft.uspto.gov/netahtml/PTO/search-adv.htm (searching for:
abst/“hardware accelerator” and APD/9/12/2005->9/12/2007).
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e.g., does not merely reference the HWA’s “operat[ing] in a secure mode
and a public mode” (claim 1) and “be[ing] shared by a secure application
and a public application” (claim 16). Nor does “hardware accelerator”
merely reflect a corresponding functional unit’s performance of the claimed
inventions’ save/restore operations, as contended by the Examiner (see
supra 3, Examiner block quote (quoting Ans. 17)).2 Rather, “hardware
accelerator” has intrinsic meaning that has not been addressed by the
Examiner.
For the foregoing reasons, the Examiner has failed to sufficiently
address the “hardware accelerator” limitation of claims 1 and 16.
Second Error
As reflected above, claim 1 requires a save/restore operation that
“saves all secure RAM content to non-volatile memory and . . . restores all
secure RAM content from the non-volatile memory.” Claim 16 requires a
save/restore operation that “saves the entire secure RAM portion to non-
volatile memory before the system powers off and restores the entire secure
RAM portion from the non-volatile memory when the system powers on
again.” In all rejections, the Examiner finds that Tanabiki teaches a
save/restore operation conducted between the “secure area” non-volatile
memory 51 and “integrated circuit section” non-volatile memory 41. See
Ans. 5–6 (claim 1) and 9–10 (claim 16); see also id. at 7, 8, and 10
(respective applications of Hepkin, Houha, and Irons).

2 Incidentally, there is no apparent relationship between the respective
save/restore operations and HWA’s of claims 1 and 16.
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Appellants reply:
Examiner seems to have missed the significance of Tanabiki’s
teaching that its internal memories . . . are “non-volatile” . . . [.]
As such, Tanabiki is not concerned with losing data that can
occur in “volatile” memories. As such, there is no teaching or
suggestion in Tanabiki for its system memory for storing
save/restore secure RAM instruction that, when executed,
perform a save operation that saves ALL secure RAM content
to non-volatile memory and a restore operation that restores
ALL secure RAM content from the non-volatile memory.
Reply Br. 4 (citations omitted; citing Tanabiki ¶¶ 21 and 23–24).
Appellants’ argument is persuasive, particularly insofar that the cited
disclosure of Tanabiki – namely paragraph 24 – presents no apparent
save/restore operation conducted between the cited non-volatile memories
51 and 41. And, even assuming arguendo that Tanabiki teaches such a
save/restore operation, the Examiner’s findings do not sufficiently explain
that occurrence. See In re Jung, 637 F.3d 1356, 1362 (Fed. Cir. 2011)
(addressing the notice requirement of rejections).
For the foregoing reasons, the Examiner has failed to sufficiently
address the “save/restore” limitation recited by independent claims 1 and 16
and incorporated by remaining claims 3–8 and 18–22 via their dependencies
from claims 1 and 16. Accordingly, we reverse the anticipation rejection of
claim 1 and its dependent claims 3 and 4 over Tanabiki. For similar reasons,
we reverse the obviousness rejections of: claims 5–7 over Tanabiki and
Hepkin; claim 8 over Tanabiki and Houha; and claims 16 and 18-22 over
Tanabiki and Irons.

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DECISION
The Examiner’s decision rejecting claims 1, 3–8, 16, and 18–22 is
reversed.
REVERSED

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