Ex Parte 7402855 et al

Patent Trial and Appeal Board

Oct 11, 2012

95001359 (P.T.A.B. Oct. 11, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,359 05/21/2010 7402855 384848904 9398
20350 7590 10/12/2012
KILPATRICK TOWNSEND & STOCKTON LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO, CA 94111-3834
EXAMINER
KIELIN, ERIK J
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
10/12/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
______________

KILOPASS TECHNOLOGY, INC.,
Third Party Requester and Appellant

v.

SIDENSE CORPORATION
Patent Owner and Respondent
______________

Appeal 2012-008939
Reexamination Control No. 95/001,359
Patent 7,402,855 B2
Technology Center 3900
______________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM,
and KEVIN F. TURNER, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL
Third Party Requester, Appellant Kilopass Technology, Inc., appeals
under 35 U.S.C. §§ 134(c) and 315(b)(1) from the Examiner’s decision
not to adopt or maintain any of Appellant’s proposed rejections of claims 1-
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11 of U.S. Patent 7,402,885 B2. Patent Owner, Respondent Sidense
Corporation,

disputes Appellant’s contentions.
We have jurisdiction under 35 U.S.C. §§ 134 and 315.
We reverse the Examiner’s decision to confirm claims 1-11.

STATEMENT OF THE CASE
Appellant appeals the Examiner’s refusal to adopt or maintain the
following 35 U.S.C. § 103(a) rejections proposed by the Requester:
Claim 1 as obvious based on Peng, U.S. 6,940,751 B2
(Sept. 6, 2005); either Curd, U.S. 6,121,795 (Sept. 19, 2000) or Nguyen,
U.S. 6,429,686 B1 (Aug. 6, 2002); and either Oh, U.S. 5,396,465 (Mar. 7,
1995) or admitted prior art (APA).
Claims 2-4 as obvious based on Peng, either Curd or Nguyen, Oh, and
APA.
Claim 1 as obvious based on Peng and Kim, U.S. 2004/0076070 A1
(Apr. 22, 2004).
Claims 2-4 as obvious based on Peng, Kim, and APA.
Claims 5-11 as obvious based on Peng, Oh, Nguyen, or Curd.
(Compare RAN 15 with App. Br. 4-5 (issues 7 and 8).)
1

1
The Examiner maintains that the claim rejections were not properly
proposed while Appellant indicates that claims 9 and “5-8 and 10-22 [sic:
10-11]” are on appeal. Further discussion follows.
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Claim 1 follows:

1. An anti-fuse memory array comprising:
a plurality of anti-fuse transistors arranged in rows and columns, each
anti-fuse transistor including:
a polysilicon gate over a channel region in a substrate, the channel
having a preset length;
a diffusion region proximate to a first end of the channel region;
a variable thickness gate oxide between the polysilicon gate and the
substrate, the variable thickness gate oxide having a thick gate
oxide portion extending from the first end of the channel region to a
predetermined distance of the preset length, and a thin gate oxide
portion extending from the predetermined distance to a second end
of the channel region,
an oxide breakdown zone proximate to the second end of the channel
region fusible to form a conductive link between the polysilicon gate
and the channel region;
bitlines coupled to the diffusion regions of a column of anti-fuse
transistors;
a sense amplifier coupled to a pair of the bitlines through isolation
devices, said isolation devices including transistors, each having a gate
oxide corresponding to said thick gate oxide portion; and wordlines coupled
to the polysilicon gates of a row of anti-fuse transistors.

(See App. Br. 19 - Claims Appx. (reformatted and emphasis
added).)

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The ‘855 Patent
The ‘855 patent describes an array of one time programmable (OTP)
anti-fuse memory devices. Each anti-fuse transistor has a variable gate
oxide 102 (underneath a polysilicon gate 106) – variable because the oxide
consists of a thick gate oxide region and a thin gate oxide region. (See
Abstract; Fig. 4.)
Figure 4 of the '855 patent appears next.

Figure 4 shows the anti-fuse transistor 100 with the variable thickness
gate oxide 102 formed on a substrate 104. (See col. 9, lines 14-20.)
The gate thin oxide region essentially acts as a localized voltage
breakdown region as compared to the thick oxide region which acts to block
voltage breakdown. (See Abstract, col. 8, lines 13-34; col. 9, ll. 27-33.)
Each anti-fuse transistor can be programmed by individually rupturing, with
a sufficiently high voltage, the thin portion of the variable thickness gate
oxide region. Such rupturing establishes a permanent conductive link (i.e.,
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an “antifuse”) at the thin portion of the gate oxide. Current through the
conductive link can be sensed by conventional sense amplifier circuits.
(Abstract, col. 10, ll.13-23; col. 13, lines 55-64.)
The sense amplifiers can be isolated by isolation transistors 704 which
also have gate oxides. (See Figure 11A.) A disclosed embodiment has equal
gate oxide thicknesses for the isolation transistors and the thick portion of
the gate oxide of the anti-fuse transistor. (See col. 13, ll. 29-33.)
DISCUSSION
During reexamination, claims are given the broadest reasonable
interpretation consistent with the specification and limitations in the
specification are not read into the claims. See In re Yamamoto, 740 F.2d
1569 (Fed. Cir. 1984).
Independent claim 1 requires that the isolation transistor gate oxides
“correspond[] to said thick gate oxide portion” of the anti-fuse transistors.
Respondent does not specify what “corresponding” means in claim 1, and
argues for example, that “none of these references even suggest that the two
oxides have the same thickness, or that there is some relationship between
the two gate oxides due to breakdown characteristics.” (Resp. Br. 10
(emphasis added).) Appellant urges that “corresponding” does not
necessarily mean that the two gate oxides have exactly the same thickness,
but maintains that the term is broad enough to include two oxides which
each prohibit voltage breakdowns at about the same circuit voltage. (See
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App. Br. 10-11 (discussing the Examiner’s claim interpretation and citing
RAN 11).)
In comparison to claim 1, claim 9 recites “the thick gate oxide portion
being identical to a gate oxide of a high voltage transistor formed on the
substrate” and also recites that “the isolation devices . . . each hav[] a gate
oxide that is the same as the thick gate oxide portion.” (Claim 9, emphasis
added.) Respondent does not present a separate argument for claim 9.
Assuming for the sake of argument that “identical” and “the same as” refers
to the respective gate oxide thicknesses, claim 9 indicates, by claim
differentiation with respect to claim 1, that claim 1 does not require the two
gate oxides to have the same thickness. In other words, claim 1 is broader
than claim 9. This interpretation comports with Respondent’s vague
argument about “some relationship” required in claim 1 between the two
oxides and also comports with Appellant’s claim interpretation.
Under Yamamoto, and pursuant to Appellant’s interpretation, claim 1
is broad enough to encompass different thicknesses in which relatively
thicker gate oxides prevent voltage breakdown as compared to thinner gate
oxide regions. In any event, as discussed below, Appellant shows error in
the Examiner’s confirmation of claim 1 under both the narrow and broad
claim interpretations of “corresponding.”
The Examiner maintains that the Requester (now Appellant) failed to
present a prima facie case that the proposed combination suggests that an
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anti-fuse transistor and an isolation transistor have the same gate oxide
thickness. The Examiner reasons as follows:
[W]hile Examiner is not saying that Requester is necessarily
wrong to suggest that it would be obvious to make the isolation
transistors' gate oxide the same as that gate oxide thickness
“corresponding to” the thick portion of the anti-fuse array,
Examiner is saying that Requester has failed to set forth a prima
facie case of obviousness based on Peng, Oh, APA, and Curd.
(RAN 10 (emphasis added).)
The Examiner also reasons as follows:
Examiner agrees with Requester that it is very well known in
the art to make gate oxides of differing thickness using
consolidated steps and that some transistors would share the
same oxide thicknesses. Nonetheless, the[re] is no teaching of
record to make the gate oxides of the isolation transistors to be
the same thickness as that of the memory cell transistors.
(RAN 10-11 (first emphasis added).)
Appellant relies on Curd’s teachings as follows:
Curd teaches that “the isolation transistor is formed with a
thicker gate oxide . . . thereby allowing the isolation transistor
to withstand input voltages that are greater than the Vcc of the
IC device without damage. . . . [T]he isolation transistor is
produced during the same process steps that are used to produce
high voltage programming transistors associated with the non-
volatile memory cells.”
(App. Br. 8 (quoting Curd at col. 3, ll. 42-56).)
The above-quoted Curd passage concludes as follows: “Therefore,
the isolation transistor is implemented without . . . changing established
process steps.” (Curd, col. 3, ll. 55-56.)
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Hence, Appellant and the Examiner agree, and the record supports,
that making gate oxides in different transistors the same thickness was well
known for consolidating process steps. (Accord App. Br. 10 (also citing Van
Buskirk Declaration to corroborate the proposition).) Appellant also
persuasively characterizes the quoted Curd passage as teaching, inter alia,
“that the isolation transistors should have thick oxide regions to withstand
high voltages – i.e., to avoid breakdown.” (See App. Br. 10 (citing Curd at
col. 3, ll. 42-46).)
However, the Examiner reasons that Curd only teaches (i.e., discloses)
that the isolation transistor and the programming transistors have the same
gate oxide thickness, and therefore, “it cannot be concluded that Curd
teaches that the isolation transistors have a gate oxide corresponding to the
thick oxide portion of the antifuse transistors of the memory array in Peng.”
(See RAN 10.)
The Examiner’s view of what Curd “teaches” overly restricts what
Curd fairly would have suggested to skilled artisans. Since the Examiner
finds (in agreement with Appellant) that it was well known that making
different gate oxides the same gate thickness would save process steps,
limiting that generic principle only to what Curd specifically discloses about
gate and programming transistors, implies that ordinarily skilled artisans
lack creativity and common sense as automatons - as Appellant essentially
argues. (See, e.g., Reb. Br. 5.) Still further, as indicated supra, Appellant
articulates specific reasons for implementing this generic teaching of equal
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thickness gate oxides to the anti-fuse and isolation transistors – i.e., both
gate oxides must maintain a certain isolation voltage to avoid punchtrough
(i.e., and/or voltage breakdown) and that it was well known that gate oxide
thickness controls the breakdown voltage. It follows that it would have been
obvious to make the two gate oxides the same thickness so that they would
withstand the same undesirable voltage levels presented in their common
circuit and so that manufacturing process steps would be minimized.
Peng, like the ‘885 patent, teaches a thick gate oxide portion of an
antifuse device for avoiding breakdown at that portion, while allowing it at
the thin gate oxide portion (to create an antifuse; i.e., conductive link, at the
thin portion). (See App. Br. 6-7 (citing Peng at Fig. 16 and col. 12, ll. 42-
65).) Since Curd teaches a thick gate oxide in an isolation transistor for
avoiding breakdown, Peng’s thick gate oxide region avoids breakdown,
circuits typically use the same voltage, and making different transistors with
the same gate oxide thickness saves process steps, it would have been
obvious to make the thick gate oxide portion of Peng’s antifuse transistor the
same thickness as the thick gate oxide of the isolation transistor.
Respondent counters that “the two gate oxides need not be the same
thickness in order for them to be able to avoid breakdown. That is, they can
be of different thicknesses in order for them to be able to avoid breakdown.”
(Resp. Br. 11.) This argument does not refute the fact that skilled artisans
knew that the same oxide thicknesses could be employed to control the same
breakdown voltages. Moreover, the ‘885 patent observes that “[i]n a typical
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CMOS process, the diffusion regions, LDD and channel implantation are
different for thin gate oxide transistors and thick gate oxide transistors.”
(‘885 patent, col. 10, ll. 58-60 (emphasis added).) This reference to two
“typical” CMOS thicknesses – i.e., “thin” and “thick” – corroborates that the
principal relationship between voltage breakdown and oxide thickness was
well known and that thickness is simply relative as it pertains to desired
voltages versus undesired breakdown voltages.
Respondent also counters that the notion of saving process steps by
making the gate oxides of the “memory cells” and the “isolation transistors
to be the same” was “lifted directly” from the ‘855 Patent. (Resp. Br. 12.)
This counter argument does not refute the Examiner’s finding and
Appellant’s rationale based inter alia on Curd that skilled artisans knew that
making two gate oxides of two different transistors the same thickness
would save process steps. In addition to Curd, as indicated supra, Appellant
also relies on the Van Buskirk Declaration for the known proposition. See
App. Br. 10 (citing Van Buskirk Decl. at ¶ 9 (“The goal of a good design is
to minimize process steps and ‘reuse’ masks and other process steps.”).)
VanBuskirk corroborates what Curd teaches – the common sense notion that
making things the same way saves process steps.
Respondent also observes that Peng requires “processing steps that are
not available in standard CMOS processes” and that the ‘855 patent only
uses standard CMOS steps. (See Resp. Br. 3; accord id. at 9-10.)
Respondent does not clarify how this observation shows unobviousness.
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Also, the claims are not limited to CMOS processes and Peng discloses
CMOS processes throughout. (See, e.g., Peng, col. 5, ll. 53-57; col. 7, ll. 23-
33; accord Van Buskirk Declaration ¶ 8.) Moreover, the ‘855 patent does
not appear to be limited to standard CMOS processes: “Those skilled in the
art will understand that the invention equally applies to all other bulk MOS,
thin film and SOI technologies including DRAM, EPROM, EEPROM and
Flash . . . .” (‘885 patent, col. 17, ll. 58-61.)
The Examiner indicates that claims 2-4 are allowable for the same
reasons as claim 1. (RAN 14.) Appellant outlines why the added limitations
of claims 2-4 would have been obvious. (App. Br. 11-12) Respondent does
not argue claims 2-4 separately. (See Resp. Br. 5, 11 (grouping e.g., claims
1-8 together).) Based on the foregoing discussion of claim 1, the Examiner
erred by not maintaining the rejection of claims 1-4 based on Peng, Curd, Oh
and APA.
Respondent does not present separate arguments with respect to the
rejection based on Peng and Kim. (See Resp. Br. 12.) Based on the
foregoing discussion of Peng, Curd, and APA, the Examiner also erred by
not maintaining the rejection of claim 1 based on Peng and Kim and claims
2-4 based further on APA.
Respondent indicates that the issues involving the rejections based on
Peng and Nguyen and the alternative rejections based on Peng and Curd
involve similar arguments. (See Resp. Br. 11-12.) However, the Examiner,
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Respondent, and Appellant separately address the teachings of Nguyen.
(See RAN 12, Resp. Br. 11-12, App. Br. 12-13.)
The Examiner finds that Nguyen teaches different thicknesses for gate
oxides. (See RAN 12.) The Nguyen passage quoted by the Examiner shows
four different gate oxide thicknesses (50, 70, 100, and 150 Angstroms). (See
RAN 12 (quoting Nguyen and citing paragraph bridging cols. 1-2).) But in
the same passage quoted by the Examiner, Nguyen also “‘[n]ote[s] that the
thickness of the oxide between the control gate of such a memory cell and
the floating gate is typically [i.e., apparently, in the prior art] 150
angstroms’” and teaches that “‘the gate oxide thickness of 150 Angstroms is
used for transistors transferring the large voltages.’” (See RAN 12 (quoting
Nguyen as noted supra, Examiner’s emphasis removed).)
Therefore, while Nguyen teaches four different gate oxide thicknesses
for different transistor types, Nguyen notes that large prior art voltage
transistors and memory devices typically had the same gate oxide thickness.
As Appellant explains, “one skilled in the art looking at Peng and Nguyen
would be motivated to at least try making the thickness of both transistor
types the same in order to prevent breakdown and to limit the number of
different CMOS processing steps required to make the integrated circuit.”
(See App. Br. 13.)
As indicated supra (see note 1), Appellant appeals a proposed
obviousness rejection of claims 5-11 based on Peng, Oh, and Nguyen or
Curd. (See App. Br. 4-5.) Respondent does not argue claims 5-11
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separately. (See Resp. Br. 5, 11, 12.) While the Examiner reasons that the
Requester had not properly proposed rejections for claims 5-11, the
Examiner agrees with Respondent that “Claims 5-11 are patentable for
basically the same reasons as for independent claim 1.” (RAN 15.)
Under 37 C.F.R. § 41.77(b), “should the Board have knowledge of
any grounds not raised in the appeal for rejecting any pending claim, it may
include in its opinion a statement to that effect with its reasons for so
holding, which statement shall constitute a new ground of rejection of
the claim.” Since this Decision constitutes a new ground of rejection for
claims 1-4 and holds that the Examiner erred with respect to claim 1, and the
parties agree that claim 1 dictates the confirmance of claims 2-11, the record
warrants a reversal of the Examiner’s decision to confirm claims 5-11
pursuant to the Board’s discretionary authority under 37 C.F.R. § 41.77(b) to
enter a new ground of rejection. In other words, any procedural deficiencies
asserted by the Examiner with respect to Requester’s proposed rejection of
claims 5-11 based on Peng, Oh, and Nguyen or Curd are rendered moot
since the Board is entering a new ground based on the recorded positions of
the parties.
2

2
The Board declines to perfect the proposed rejection of the new claims 5-
11 by matching claim elements with the prior art. Such elements were not
argued separately as indicated supra. It is also noted that Appellant
provided additional reasons to support the obviousness of claims 5-11 in its
Third Party Requestor’s Comments . . . in Inter Partes Reexamination of
U.S. Patent No. 7,402,855 12-16 (Nov. 4, 2010) and in its Brief (App. Br.
(Continued on next page.)
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Based on the foregoing discussion, the Examiner’s decision to
confirm claims 1-11 is reversed. In accordance with 37 C.F.R. § 41.77(a)
and (b), and as discussed, reversal of the Examiner’s determination
constitutes a NEW GROUND OF REJECTION.
CONCLUSION
This decision contains a new ground of rejection pursuant to
37 C.F.R. § 41.77(b), which provides that “[a]ny decision which includes a
new ground of rejection pursuant to this paragraph shall not be considered
final for judicial review.” Correspondingly, no portion of the decision is
final for purposes of judicial review. A requester may also request rehearing
under 37 C.F.R. § 41.79, if appropriate; however, the Board may elect to
defer issuing any decision on such request for rehearing until such time that
a final decision on appeal has been issued by the Board.
For further guidance on new grounds of rejection, see 37 C.F.R.
§ 41.77(b)-(g). The decision may become final after it has returned to the
Board. 37 C.F.R. § 41.77(f).
37 C.F.R. § 41.77(b) also provides that the Patent Owner, WITHIN
ONE MONTH FROM THE DATE OF THE DECISION, must exercise one
of the following two options with respect to the new grounds of rejection to
avoid termination of the appeal as to the rejected claims:

15-17). On the other hand, Respondent does not argue the claims separately
from claim 1 or otherwise contest the procedural propriety of the proposed
rejections.
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(1) Reopen prosecution. The owner may file a response requesting
reopening of prosecution before the examiner. Such a response must be
either an amendment of the claims so rejected or new evidence relating to
the claims so rejected, or both.
(2) Request rehearing. The owner may request that the proceeding be
reheard under § 41.79 by the Board upon the same record. …
Any request to reopen prosecution before the examiner under
37 C.F.R. § 41.77(b)(1) shall be limited in scope to the “claims so rejected.”
Accordingly, a request to reopen prosecution is limited to issues raised by
the new ground(s) of rejection entered by the Board. A request to reopen
prosecution that includes issues other than those raised by the new ground(s)
is unlikely to be granted. Furthermore, should the patent owner seek to
substitute claims, there is a presumption that only one substitute claim would
be needed to replace a cancelled claim.
A requester may file comments in reply to a patent owner response.
37 C.F.R. § 41.77(c). Requester comments under 37 C.F.R. § 41.77(c) shall
be limited in scope to the issues raised by the Board’s opinion reflecting its
decision to reject the claims and the patent owner’s response under
paragraph 37 C.F.R. § 41.77(b)(1). A newly proposed rejection is not
permitted as a matter of right. A newly proposed rejection may be
appropriate if it is presented to address an amendment and/or new evidence
properly submitted by the patent owner, and is presented with a brief
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explanation as to why the newly proposed rejection is now necessary and
why it could not have been presented earlier.
Compliance with the page limits pursuant to 37 C.F.R. § 1.943(b), for
all patent owner responses and requester comments, is required.
The examiner, after the Board’s entry of a patent owner response and
requester comments, will issue a determination under 37 C.F.R. § 41.77(d)
as to whether the Board’s rejection is maintained or has been overcome. The
proceeding will then be returned to the Board together with any comments
and reply submitted by the owner and/or requester under 37 C.F.R.
§ 41.77(e) for reconsideration and issuance of a new decision by the Board
as provided by 37 C.F.R. § 41.77(f).
Extensions of time for taking action under 37 C.F.R. § 41.77(b) are
governed by 37 C.F.R. § 41.77(g). See also 37 C.F.R. § 41.77 regarding
extensions of time for requesting rehearing.

REVERSED;
37 C.F.R. § 41.77(b)

ak

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Kilpatrick Townsend & Stockton, LLP
Two Embarcadero Center
Eighth Floor
San Francisco, CA 94111

Third Party Requester:
Perkins Coie, LLP
Patent – SEA
P.O. Box 1247
Seattle, WA 98111-1247