Ex Parte 7,330,953 et al

Board of Patent Appeals and Interferences

Sep 11, 2012

95001201 (B.P.A.I. Sep. 11, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,201 06/23/2009 7,330,953 2805.002REXA 1873
26111 7590 09/12/2012
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
CHOI, WOO H
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
09/12/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

NVIDIA CORPORATION
Requester, Respondent
v.

RAMBUS, INC.
Patent Owner, Appellant
____

Appeal 2012-003804
Inter partes Reexamination Control No. 95/001,201
Patent 7,330,953 B2
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

SIU, Administrative Patent Judge.

DECISION ON APPEAL
Appellant, patent owner Rambus, Inc., appeals under 35 U.S.C. §§
134(b) and 315(a) from a Right of Appeal Notice rejecting claims 1-28.1

1 Respondent and Third-Party Requester (NVIDIA Corporation) “withdraws
its appeal to the Board, including all of its appeal briefs and supporting
papers” (“Notice of Withdrawal of Third-Party Requester’s Appeal and
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We have jurisdiction under 35 U.S.C. §§ 134 and 315. An oral hearing was
conducted on August 15, 2012.

STATEMENT OF THE CASE
This proceeding arose from a request by NVIDIA Corporation for an
inter partes reexamination of U. S. Patent 7,330,953 B2 (the ‘953 patent),
entitled “Memory System Having Delayed Write Timing,” and issued to
Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel,
Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, and David
Nguyen (February 12, 2008).
The ‘953 patent describes memory devices including “[m]atching the
timing of the write-use of the data resource to the read-use of the data
resource” (col. 10, ll. 49-50). Claim 1 on appeal reads as follows:
1. A system comprising:
a first set of interconnect resources to convey:
a sense command; and
after the sense command, a write command that specifies a write
operation;
a second set of interconnect resources to convey:
a row address that identifies a row of a memory array to sense in
response to the sense command; and
after the row address, a column address that identifies a column
location of the row;
a third set of interconnect resources to convey data; and
a memory device comprising:

Other Papers,” filed February 17, 2012, p. 1). In view of Third-Party
Requester’s withdrawal from these proceedings, we need not consider issues
set forth in Third-Party Requester’s cross appeal (i.e., Third Party
Requester’s Cross-Appeal Brief in Inter Partes Reexamination Pursuant to
37 C.F.R. § 41.67, filed September 16, 2011) and associated briefs and
papers.
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a memory core including a plurality of memory cells;
a first set of pins coupled to the first set of interconnect resources, the
first set of pins to receive the sense command and the write command,
wherein after a first delay time transpires from when the write command is
received at the first set of pins, the memory device applies a control signal to
convey a plurality of data bits to the column location, in response to the
write command;
a second set of pins coupled to the second set of interconnect
resources, the second set of pins to receive the row address and the column
address; and
a third set of pins coupled to the third set of interconnect resources,
the third set of pins to receive the plurality of data bits after a second delay
time has transpired from when the write command is received at the second
set of pins.

(App. Br. 37-38, Claims Appendix.)

The Examiner relies on the following prior art references:
Ware US 5,430,676 Jul. 4, 1995
Ryan US 6,044,429 Mar. 28, 2000
Gillingham US 6,088,774 Jul. 11, 2000
Gustavson US 6,226,723 B1 May 1, 2001
Inagaki JP 57-210495 Dec. 24, 1982

JEDEC Standard, Configurations for Solid State Memories, JEDEC
Standard No. 21-C, Release 4, November 1993 (“JEDEC”).

Shigeo Ohshima and Tohru Furuyama, “High Speed DRAMs with
Innovative Architectures,” IEICE Trans. Electron., Vol. E77-C, No. 8,
August 1994 (“Ohshima”).

The Examiner rejects the claims as follows:
Claims 1, 2, 10, 12, 13, 18, 20-22, and 24 under 35 U.S.C. § 102(b) as
anticipated by Ware.
Claims 11, 17, and 28 under 35 U.S.C. § 102(e) as anticipated by
Gillingham.
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Claims 3 and 23 and claims 3, 11, 17, 19, 23, and 28 under 35 U.S.C.
§ 103(a) as unpatentable over the combination of Gillingham and Ohshima
and the combination of Gillingham and Ryan, respectively.
Claims 4-9, 14-16, and 25-27 under 35 U.S.C. § 103(a) as
unpatentable over the combination of Ware and any one of Gustavson or
Ohshima.
Claims 1, 2, 10, 12, 13, 18, 20-22, 24, and 25; claims 4-9, 14-16, 26,
and 27; and claims 4-9 and 16 under 35 U.S.C. § 103(a) as unpatentable over
the combination of JEDEC and Ware; the combination of JEDEC, Ware, and
Gustavson; and the combination of JEDEC Ware, and Inagaki, respectively.

ISSUE
Did the Examiner err in rejecting claims 1-28?

FINDINGS OF FACT
1) Ware discloses “latency between the clock cycle with the . . .
write command and the clock cycle with the first word of write data is zero”
but that “there is a delay of tCAA which occurs [for a read command]” (col. 8,
ll. 52-55).
2) Ware discloses that because of “wasted clock cycles” (col. 8, l.
56) when the write latency is zero, “the write latency is made programmable
so that is can be adjusted to equal the read latency” (col. 8, ll. 59-61).
3) Ware discloses an example of programming latency in which
“DRAM control logic 500 . . . delays a signal to initiate an operation (Start
R/W) 505 a certain number of clock cycles . . . dependent upon the
information loaded into the latency control register 510” (col. 8, ll. 63-67;
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Fig. 17) to “determine whether the signal 505 is immediately input or input
after a predetermined delay . . .” (col. 9, ll. 6-7).

PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted).
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co. of Kansas City,
383 U.S. 1, 17-18 (1966).
“The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).

ANALYSIS
Ware Reference - Anticipation
The Examiner rejects claims 1, 2, 10, 12, 13, 18, 20-22, and 24 as
anticipated by Ware (RAN 11). We agree with the Examiner for at least the
reasons set forth by the Examiner (see, e.g., RAN 11-14 and 30-33).
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As the Examiner points out and as described above, Ware discloses
that when a read latency is equal to a finite value (e.g., tCAA) 2 and a write
latency is equal to zero, 3 there may be undesired “wasted clock cycles.” In
order to address this problem, according to Ware, the write latency is “made
programmable” so that the write latency may be “adjusted to equal the read
latency (FF 1-3).
Ware further discloses an example of programming the latency such
that “a signal to initiate an operation (Start R/W) 505” is delayed within
“DRAM control logic 500” (FF 1-3; Fig. 17; col. 8, ll. 63-66). Hence, Ware
discloses that a write latency is “programmed” so that “a signal to initiate an
operation (Start R/W)”4 is delayed. In other words, Ware discloses a delay
that transpires from when the write command is received (i.e., “the clock
cycle with the . . . write command” – col. 8, ll. 52-53) to when “a signal to
initiate an operation” (col. 8, ll. 64-65) (i.e., the write operation) is applied.
This process is further illustrated in Fig. 17 where a signal to “initiate read or
write sequence” is delayed within the DRAM logic (element 500, Fig. 17).
Appellant has not sufficiently pointed out any differences between these
features disclosed by Ware and the presently claimed invention since claim 1
recites and Ware discloses a delay between when the write command is
received to when a signal is applied.

2 The time measured “between the clock cycle with the . . . read command
and the clock cycle with the first word of read data” (col. 8, ll. 47-49).
3 The time measured “between the clock cycle with the . . . write command
and the clock cycle with the first word of write data” (col. 8, ll. 52-54).
4 Col. 8, ll. 64-65 – in this case, a signal responsive to the write command
since Ware discloses this “exemplary structure” for programming the write
latency “so that it can be adjusted to equal . . . the read latency” (col. 8, ll.
60-61).
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Appellant argues that Ware “does not even indicate whether the
initiated operation is in response to a read or write command” and that
“nothing in . . . Ware . . . speaks to the delay of the internal application of a
control signal in response to the write command” (App. Br. 20). We
disagree. As described above, Ware addresses the problem of “wasted clock
cycles” by making a write latency “programmable” (col. 8, l. 60) and a
specific example of programming such a latency. One of ordinary skill in
the art would have understood that the “latency” (or delay) being
programmed in the specific example of Ware (the specific example
immediately following and flowing from Ware’s description of the problem
in which Ware explicitly discloses that a write latency needs to be
programmed) is a write latency (see, in general, col. 8, ll. 52-67).
Appellant argues that “the latency control register 510 [of Ware, Fig.
17] is . . . the claimed second delay [and, therefore, not the first delay as
recited in claim 1]” (App. Br. 22). Claim 1 recites a second delay measured
from when the write command is received to when a plurality of data bits
(i.e., write data) is received. Appellant has not sufficiently demonstrated
that the “latency control register 510” of Ware creates the “second delay” as
recited in claim 1 as opposed to the “first delay” as recited in claim 1. More
importantly, Appellant has not sufficiently demonstrated that Ware fails to
disclose the first delay and the second delay as recited in claim 1.
The “latency control 510” (Fig. 17) of Ware determines “whether the
signal 505 is immediately input or input after a predetermined delay” (col. 9,
ll. 6-7), the signal being used to “initiate read or write sequence[s]” (see
bottom of Fig. 17) within the DRAM control logic 500 (col. 8, ll. 63-64 and
Fig. 17). Hence, the “latency control register” of Ware causes a delay in the
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application of a signal (i.e., signal 505) after which a write sequence is
initiated (i.e., the first delay as recited in claim 1) rather than when write
data is received (i.e., the second delay as recited in claim 1).
Appellant does not provide additional arguments in support of claims
10, 12, 13, 18, 20-22, and 24 (App. Br. 23-24). The Examiner did not err in
rejecting claims 1, 2, 10, 12, 13, 18, 20-22, and 24 as anticipated by Ware.

Gillingham Reference
Claim 11 recites a predetermined write delay time that is a channel
turnaround time less than the predetermined read delay time. Claims 3, 17,
19, 23, and 28 recite similar features. The Gillingham reference (U.S. Patent
No. 6,008,774 – the ‘774 patent) was filed September 19, 1997 (issued July
11, 2000) and is related to U.S. Provisional Applications 60/026,594
(September 20, 1996); 60/055,349 (August 11, 1997), and 60/057,092
(August 27, 1997). While the Examiner states that Gillingham (the ‘774
patent) discloses a write delay time that is a channel turnaround time less
than the predetermined read delay time (RAN 10), the Examiner appears to
agree that U.S. Provisional Application 60/026,594 does not disclose this
feature, thus according the Gillingham reference the priority date of August
11, 1997.
Appellant provides a Declaration by “the assignee of [the ‘953
patent]” (Declaration of Craig E. Hampel under 37 C.F.R. § 1.131, filed
April 2, 2010, ¶ 2), which states that the inventors of the ‘953 patent
“conceived of the inventions claimed in the [‘953 patent]” prior to January 2,
1997 and “continued diligently from prior to January 2, 1997 to October 10,
1997, which is the earliest filing date of [the ‘953 patent]” (Declaration of
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Craig E. Hampel under 37 C.F.R. § 1.131, filed April 2, 2010, ¶ 14). The
Examiner appears to agree with Appellant, however, regarding claims 3, 11,
17, 19, 23, and 28 (which recite a write delay time that is a channel
turnaround time less than a read delay time, or similar feature), the Examiner
states that Appellant “has failed to explain how 9-cycle read delay [as seen
in the “Davis email – Exhibit CA] was obtained from the timing diagram
that shows a 12-cycle delay” (RAN 21, citing Davis email – Exhibit CA). In
other words, the Examiner finds that Appellant has merely demonstrated
prior conception and reduction to practice or diligence with constructive
reduction to practice of a write delay time (e.g., of 8 cycles – Davis email)
that is less than a channel turnaround time (of 1 cycle – Davis email) less
than a read delay time (of 12 cycles – Davis email) rather than a write delay
time (e.g., of 8 cycles – Davis email) that is a channel turnaround time (of 1
cycle – Davis email) less than a read delay time (of 9 cycles – Davis email),
as required by claims 3, 11, 17, 19, 23, and 28.
We disagree with the Examiner for at least the reasons set forth by
Appellant (App. Br. 29-31). As Appellant points out, the Davis email
appears to show the disputed claimed feature at least with the specific
example described in the Davis email of a write delay time of 8 cycles being
equal to a read delay time of 9 cycles minus a channel turnaround time of 1
cycle (see, e.g., App. Br. 29-31).
The Examiner erred in rejecting claims 11, 17, and 28 as anticipated
by Gillingham and claims 3, 11, 17, 19, 23, and 28 as unpatentable over
Gillingham any one of Ohshima or Ryan.

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Obviousness Rejections
The Examiner rejects claims 4-9, 14-16, and 25-27 as unpatentable by
the combination of Ware and any one of Gustavson or Ohshima (RAN 14-
16) and claims 4-9, 14-16, 26, and 27 as unpatentable over Ware, Gustavson,
and JEDEC. Appellant provides the same arguments in support of claims 4-
9, 14-16, and 25-27 over the combination of Ware and Ohshima as those
provided in support of claims 1, 2, 10, 12, 13, 18, 20-22, and 24 as addressed
above. For at least the reasons set forth above, the Examiner did not err in
rejecting claims 4-9, 14-16, and 25-27 as unpatentable over Ware and
Ohshima.
Since Appellant has not sufficiently demonstrated that the Examiner
erred in rejecting claims 4-9, 14-16, and 25-27 as unpatentable over Ware
and Ohshima, we need not reach the issue of the propriety of the Examiner’s
rejection of these claims over Ware and Gustavson (and JEDEC). Cf. In re
Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching rejections after
finding another rejection to be upheld).
Appellant argues that none of claims 1-28 would have been obvious to
one of ordinary skill in the art over any combination of references because
“there is substantial evidence of . . . secondary considerations, that outweigh
against any finding of obviousness under 35 U.S.C. § 103(a)” (App. Br. 31),
which, according to Appellant, “include commercial success and licensing of
others to use the patented invention” (App. Br. 32). However, the weight
given to evidence of secondary considerations is dependent upon whether
there is a nexus between the merits of the claimed invention and the
evidence offered. Stratoflex, Inc. v. Aeroquip Corp., 713 F.2d 1530, 1539
(Fed. Cir. 1983). In the present case, we agree with the Examiner that
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Appellant has failed to adequately demonstrate a nexus since Appellant does
not provide sufficient evidence that clearly connects the alleged commercial
success to the merits of the claimed invention.
As one example, Appellant has not sufficiently established that the
sale of “500 million memory devices incorporating the Rambus . . . memory
interface” (App. Br. 32) constitutes “commercial success” when considered
in relation to overall market share. In fact, Appellant does not appear to
provide any data pertaining to overall market share. Even assuming that the
sale of “500 million memory devices” would have constituted “commercial
success as Appellant argues, Appellant has merely alleged that “500 million
memory devices” “incorporated” the “Rambus . . . memory interface.” (Id.
at 32) Appellant has not adequately demonstrated that any of the “500
million memory devices” were sold because of the “Rambus . . . memory
interface” supposedly contained therein. In other words, Appellant does not
establish a nexus between the patented invention and the alleged commercial
success. (Id.)
Appellant argues that “Rambus has extensively licensed the ‘953
patent” (App. Br 32). As above and as pointed out by the Examiner,
Appellant does not provide an adequate showing that a nexus exists between
the specific features of the claimed invention and the alleged licensing
activity.
Appellant states that while the Patent Owner must show some causal
relation between an invention and commercial success (citing Merck & Co.,
Inc. v. Teva Pharmaceuticals USA, Inc., 395 F.3d 1364, 1376 (Fed. Cir.
2005)), the Patent Owner, according to Appellant, need not demonstrate that
“the claimed invention must be the sole cause of the commercial success”
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(App. Br. 33). Even assuming this allegation to be true, Appellant has not
established the required nexus between the claimed invention and any
alleged commercial success (or licensing). We agree with Appellant’s
implication that Appellant failed to demonstrate that the claimed invention
was the “sole” cause of any potential commercial success (or licensing).
More importantly, however, without an adequate showing of a nexus
between the claimed invention and any alleged commercial success (or
licensing), Appellant has failed to adequately demonstrate that “the claimed
invention” was a cause of the commercial success (assuming that
commercial success even occurred) or that the specific features of the
claimed invention was in any way related to any commercial success (or
licensing) that might (or might not) have occurred. (Id.)5

Appellant does not provide additional arguments in support of claims
1, 4-10, 12-16, 18, 20-22, or 24-27, or arguments with respect to Ware in
combination with any of Ohshima, JEDEC, or Inagaki.

5 “Instead, the applicant must submit some factual evidence that
demonstrates the nexus between the sales and the claimed invention-for
example, an affidavit from the purchaser explaining that the product was
purchased due to the claimed features.” In re Huang, 100 F.3d 135, 140
(Fed. Cir. 1996) (Reasoning that Huang had not carried the burden of
demonstrating nexus where “Wilson may have bought the grips due to lower
manufacturing costs, the market position of Huang's company, prior
relations between the two companies, or features of the product attractive to
Wilson but unrelated to the patented subject matter.”)
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CONCLUSION
The Examiner erred in rejecting claims 3, 11, 17, 19, 23, and 28 over
Gillingham (alone or in combination with Ohshima or Ryan) but the
Examiner did not err in rejecting claims 1, 2, 4-9, 10, 12-16, 18, 20-22, 24-
27 over Ware (alone or in combination with Ohshima, JEDEC, or Inagaki).

DECISION
The Examiner’s decision to reject claims 11, 17 and 28 as anticipated
by Gillingham; claims 3 and 23 as unpatentable over Gillingham and any
one of Ohshima or Ryan; and claims 11, 17, 19, and 28 as unpatentable over
Gillingham and Ryan is reversed.
The Examiner’s decision to reject claims 1, 2, 10, 12, 13, 18, 20-22,
and 24 as anticipated by Ware; claims 4-9, 14-16, and 25-27 as unpatentable
over Ware and Ohshima; claims 1, 2, 10, 12, 13, 18, 20-22, 24, and 25 as
unpatentable over Ware and JEDEC; and claims 4-9 and 16 as unpatentable
over Ware JEDEC and Inagaki is affirmed.
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.

AFFIRMED-IN-PART

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Patent Owner:

STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, NW
WASHINGTON, DC 20005

Third Party Requester

HAYNES AND BOONE, LLP
IP SECTION
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219