Ex Parte 7330952 et al

Board of Patent Appeals and Interferences

Sep 11, 2012

95001196 (B.P.A.I. Sep. 11, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,196 06/04/2009 7330952 2805.002REX9 8788
26111 7590 09/12/2012
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
CHOI, WOO H
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
09/12/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

NVIDIA CORPORATION
Respondent, Requester
v.

RAMBUS, INC.
Patent Owner, Appellant
____

Appeal 2012-003816
Inter partes Reexamination Control No. 95/001,196
Patent 7,330,952 B2
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

SIU, Administrative Patent Judge.

DECISION ON APPEAL
Appellant, patent owner Rambus, Inc., appeals under 35 U.S.C. §§
134(b) and 315(a) from a Right of Appeal Notice rejecting claims 1-28.1

1 Respondent and Third-Party Requester (NVIDIA Corporation) states that
“it no longer intends to participate in the present reexamination” (“Notice of
Non-Participation in Inter Partes Reexamination,” filed February 8, 2012).
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We have jurisdiction under 35 U.S.C. §§ 134 and 315. An oral hearing was
conducted on August 15, 2012.

STATEMENT OF THE CASE
This proceeding arose from a request by NVIDIA Corporation for an
inter partes reexamination of U. S. Patent 7,330,952 B2 (the ‘952 patent),
entitled “Integrated Circuit Memory Device Having Delayed Write Timing
Based on Read Response Time,” and issued to Richard M. Barth, Frederick
A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M.
Abhyankar, James A. Gasbarro, and David Nguyen (February 12, 2008).
Claim 1 on appeal reads as follows:
1. An integrated circuit memory device comprising:
a memory core including a plurality of memory cells;
a pin to receive a clock signal;
a first set of pins to receive, using the clock signal:
a write command to specify that the memory device receive
write data and store the write data in the memory core;
and
a read command to specify that the memory device output read
data accessed from the memory core, wherein the first set
of pins receive the read command after the first set of
pins receive the write command; and
a second set of pins to receive the write data after a first delay time
has transpired from when the write command is received at the first set of
pins;
the second set of pins to provide, for each pin of the second set of
pins, output of at least two bits of the read data after a second delay time
transpires from when the read command is received, wherein the at least two

We will therefore not consider issues set forth in Third-Party Requester’s
cross appeal (i.e., Third Party Requester’s Cross-Appeal Brief in Inter
Partes Reexamination Pursuant to 37 C.F.R. § 41.67, filed July 28, 2011)
and associated briefs and papers.
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bits of the read data are provided during a clock cycle of the clock signal,
wherein the second delay time is based on the first delay time, and wherein
control information to store the write data in the memory core is asserted
internally to the memory device after a third delay time has transpired from
when the write command is received and such that the third delay time is
greater than the time that transpires from when the read command is
received to when control information to output the read data is asserted
internally to the memory device.

(App. Br. 39, Claims Appendix.)

The Examiner relies on the following prior art references:
Ware US 5,430,676 Jul. 4, 1995
Ryan US 6,044,429 Mar. 28, 2000
Gillingham US 6,088,774 Jul. 11, 2000
Gustavson US 6,226,723 B1 May 1, 2001
Inagaki JP 57-210495 Dec. 24, 1982

JEDEC Standard, Configurations for Solid State Memories, JEDEC
Standard No. 21-C, Release 4, November 1993 (hereinafter “JEDEC”).

Shigeo Ohshima and Tohru Furuyama, “High Speed DRAMs with
Innovative Architectures,” IEICE Trans. Electron., Vol. E77-C, No. 8,
August 1994 (hereinafter “Ohshima”).

The Examiner rejects the claims as follows:
Claims 13, 15-17, and 26 under 35 U.S.C. § 102(b) as anticipated by
Ware.
Claim 24 under 35 U.S.C. § 103(a) as unpatentable over the
combination of Ware and Gustavson and claims 1, 3, 5, 7-9, 11, 18, 19, 21,
22, 24, 25, and 27 under 35 U.S.C. § 103(a) as unpatentable over the
combination of Ware and any one of Gustavson or Ohshima.
Claims 20 and 28; claims 14, 20, 23, and 28; and claims 2 and 6 under
35 U.S.C. § 103(a) as unpatentable over the combination of Gillingham and
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Ohshima; the combination of Gillingham and Ryan; and the combination of
Gillingham, Ryan, and Inagaki, respectively.
Claims 4 and 10 under 35 U.S.C. § 103(a) as unpatentable over the
combination of JEDEC, Gustavson, and any one of Thurston or Ware.

ISSUE
Did the Examiner err in rejecting claims 1-28?

FINDINGS OF FACT
1) Ware discloses “latency between the clock cycle with the . . .
write command and the clock cycle with the first word of write data is zero”
but that “there is a delay of tCAA which occurs [for a read command]” (col. 8,
ll. 52-55).
2) Ware discloses that because of “wasted clock cycles” (col. 8, l.
56) when the write latency is zero, “the write latency is made programmable
so that is can be adjusted to equal the read latency” (col. 8, ll. 59-61).
3) Ware discloses an example of programming latency in which
“DRAM control logic 500 . . . delays a signal to initiate an operation (Start
R/W) 505 a certain number of clock cycles . . . dependent upon the
information loaded into the latency control register 510” (col. 8, ll. 63-67;
Fig. 17) to “determine whether the signal 505 is immediately input or input
after a predetermined delay . . .” (col. 9, ll. 6-7).

PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
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claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted).
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co. of Kansas City,
383 U.S. 1, 17-18 (1966).
“The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).

ANALYSIS
Ware Reference- Anticipation
The Examiner rejects claims 13, 15-17, and 26 as anticipated by Ware
(RAN 14-16). We agree with the Examiner for at least the reasons set forth
by the Examiner (see, e.g., RAN 14-16 and 40-42).
As the Examiner points out and as described above, Ware discloses
that when a read latency2 is equal to a finite value (e.g., tCAA) and a write
latency3 is equal to zero, there may be undesired “wasted clock cycles.” In
order to address this problem, according to Ware, the write latency is “made
programmable” so that the write latency may be “adjusted to equal the read
latency (FF 1-3).

2 The time measured “between the clock cycle with the . . . read command
and the clock cycle with the first word of read data” (col. 8, ll. 47-49).
3 The time measured “between the clock cycle with the . . . write command
and the clock cycle with the first word of write data” (col. 8, ll. 52-54).
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Ware further discloses an example of programming the latency such
that “a signal to initiate an operation (Start R/W) 505” is delayed within
“DRAM control logic 500” (FF 1-3; Fig. 17; col. 8, ll. 63-66). Hence, Ware
discloses that a write latency is “programmed” so that “a signal to initiate an
operation (Start R/W)”4 is delayed. In other words, Ware discloses a delay
that transpires from when the write command is received (i.e., “the clock
cycle with the . . . write command” – col. 8, ll. 52-53) to when “a signal to
initiate an operation” (id. at. 64-65) (i.e., the write operation) is applied.
This process is further illustrated in Fig. 17 where a signal to “initiate read or
write sequence” is delayed within the DRAM logic (element 500, Fig. 17).
Appellant has not sufficiently pointed out any meaningful differences
between these features disclosed by Ware and the presently claimed
invention since claim 1 recites and Ware discloses a delay between when the
write command is received to when a signal is applied.
Regarding claim 26, Appellant argues that the “Start R/W signal is not
a write command” (App. Br. 19) but does not indicate a specialized
definition of “write command” in the Specification. In the absence of a
specific definition of the term “write command,” we construe the term
broadly but reasonably and in light of the Specification to include any
instruction or data element that specifies that a device receive write data.
This definition comports with a plain and customary meaning as would have

4 Col. 8, ll. 64-65 – in this case, a signal responsive to the write command
since Ware discloses this “exemplary structure” for programming the write
latency “so that it can be adjusted to equal . . . the read latency” (Id. at, ll.
60-61)
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been understood by one of skill in the art as well as the claim requirement
that a write command specify “that the memory device receive write data.”
As described above and as pointed out by the Examiner, Ware
discloses a “clock cycle with the . . . write command” (col. 8, ll. 52-53)
associated with a write latency that “is made programmable” (id. at, ll. 60)
by delaying “a signal to initiate an operation” (id. at, ll. 64-65). We disagree
with Appellant’s assertion that Ware fails to disclose a write command since
Ware explicitly discloses a “write command” (see, e.g., col. 8, l. 53) and an
exemplary structure in which a “Start R/W” instruction initiates an operation
that one of skill in the art would have understood to be a write operation.
Since “Start R/W” specifies that a device receive write data (i.e., initiates a
write operation), we disagree with Appellant that there is any meaningful
difference between the “Start R/W” of Ware and the claimed “write
command.”
Appellant also argues that “Ware does not disclose . . . [that] the Start
R/W signal results in a delayed internal presentation of a write command”
(App. Br. 19). Claim 26 recites presenting the write command internally
after a first delay time has transpired from when the write command was
received. As described above, Ware discloses receiving a write command
(e.g., receiving a write command in a “clock cycle with the . . . write
command” – col. 8, ll. 52-53), making the associated write latency
“programmable so that it can be adjusted” (id. at, ll. 60-61), and delaying the
“signal to initiate an operation” (id. at, ll. 64-65). Given Ware’s explicit
disclosure of delaying an instruction that specifies that a device receive write
data (i.e., delaying a “write command”), we disagree with Appellant’s
assertion.
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Appellant also argues that Ware discloses a “Start R/W signal” that
“. . . if anything, corresponds to the amount of data ‘latency’ (Murphy Decl.,
¶¶ 35, 37.)” (App. Br. 21) rather than “an internal presentation latency term”
(id. at 22). However, as described above, Ware addresses the problem of
“wasted clock cycles” by making a write latency “programmable” (col. 8, l.
60) and further provides a specific example of programming such a latency.
One of ordinary skill in the art would have understood that the “latency” (or
delay) being programmed in the specific example of Ware (the specific
example immediately following and flowing from Ware’s description of the
problem in which Ware explicitly discloses that a write latency needs to be
programmed) is a write latency (see, in general, col. 8, ll. 52-67).
Appellant also argues that “Figure 2 [of Ware] does not show any
items to delay the signals . . . nor does it show anything remotely equivalent
to the write delay block 2709 in FIG. 20 of the ‘119 patent” (App. Br. 20-
21). However, as described above, Appellant has not provided sufficient
evidence that Ware fails to disclose the claimed invention.
Claims 13 and 15-17 recite similar features as claim 26 and Appellant
does not provide additional arguments in support of these claims (App. Br.
23-24). The Examiner did not err in rejecting claims 13, 15-17, and 26 as
anticipated by Ware.

Ware Reference- Obviousness
Appellant argues that it would not have been obvious to one of
ordinary skill in the art to combine the Ware reference with any one of
Gustavson or Ohshima because “Rambus’ Direct RDRAM technology have
achieved substantial commercial success” (App. Br. 34) and “Rambus has
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extensively licensed the ‘952 patent” (id). The weight given to evidence of
secondary considerations is dependent upon whether there is a nexus
between the merits of the claimed invention and the evidence offered.
Stratoflex, Inc. v. Aeroquip Corp., 713 F.2d 1530, 1539 (Fed. Cir. 1983). In
the present case, we agree with the Examiner that Appellant has failed to
adequately demonstrate a nexus since Appellant does not provide sufficient
evidence that clearly connects the alleged commercial success to the merits
of the claimed invention.
As one example, Appellant has not sufficiently established that the
sale of “500 million memory devices incorporating the Rambus . . . memory
interface” (App. Br. 34) constitutes “commercial success” when considered
in relation to overall market share. In fact, Appellant does not appear to
provide any data pertaining to overall market share. Even assuming that the
sale of “500 million memory devices” would have constituted “commercial
success” as Appellant argues, Appellant has merely alleged that “500 million
memory devices” “incorporated” the “Rambus . . . memory interface.”
Appellant has not adequately demonstrated that any of the “500 million
memory devices” were sold because of the “Rambus . . . memory interface”
supposedly contained therein (or any specific claim features present within
the “memory interface”). In other words, Appellant does not establish a
nexus between the patented invention and the alleged commercial success.
Appellant argues that “Rambus has extensively licensed the ‘952
patent” (App. Br 34). As above and as pointed out by the Examiner,
Appellant does not provide an adequate showing that a nexus exists between
the specific features of the claimed invention and the alleged licensing
activity.
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Appellant states that while the Patent Owner must show some causal
relation between an invention and commercial success (citing Merck & Co.,
Inc. v. Teva Pharmaceuticals USA, Inc., 395 F.3d 1364, 1376 (Fed. Cir.
2005)), the Patent Owner, according to Appellant, need not demonstrate that
“the claimed invention must be the sole cause of the commercial success”
(App. Br. 35). Even assuming this allegation to be true, Appellant has not
established the required nexus between the claimed invention and any
alleged commercial success (or licensing). We agree with Appellant’s
implication that Appellant failed to demonstrate that the claimed invention
was the “sole” cause of any potential commercial success (or licensing).
More importantly, however, without an adequate showing of a nexus
between the claimed invention and any alleged commercial success (or
licensing), Appellant has failed to adequately demonstrate that “the claimed
invention” was a cause of the commercial success (assuming that
commercial success even occurred), or that the claimed invention was in any
way related to any commercial success (or licensing) that might (or might
not) have occurred. Therefore, we are not persuaded by Appellant’s
arguments pertaining to secondary considerations as they relate to the
Examiner’s obviousness rejections.5

5 “Instead, the applicant must submit some factual evidence that
demonstrates the nexus between the sales and the claimed invention-for
example, an affidavit from the purchaser explaining that the product was
purchased due to the claimed features.” In re Huang, 100 F.3d 135, 140
(Fed. Cir. 1996) (Reasoning that Huang failed to meet the initial burden of
showing nexus because “despite Huang’s personal opinion, Wilson may
have bought the grips due to lower manufacturing costs, the market position
of Huang's company, prior relations between the two companies, or features
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Regarding claims 1 and 3, Appellant argues that Ware does not
disclose “anything about the length of time before the control information is
asserted internally to store write data with respect to the length of time
between when the read command is received and before the control
information to output read data is asserted internally” (App. Br. 25). Claim
1 recites a third delay (i.e., time from when a write command is received to
the time when control information to store write data is asserted) is greater
than the time from when a read command is received to when control
information to output read data is asserted. The Examiner states that “Ware
discloses all of the limitations [of claim 1]”6 (RAN 16) but does not indicate
that either of Ware, Gustavson, or Ohshima discloses or suggests this feature
of claim 1. Ware, for example, appears to disclose adjusting a write latency
“to equal [the] read latency” (col. 8, l. 61) rather than adjusting a time
between receiving a write command and asserting a write control signal to
be less than the time between receiving a read command and asserting a read
control signal. Therefore, we agree with Appellant that Ware in
combination with either one of Gustavson or Ohshima does not disclose this
feature.
The Examiner erred in rejecting claims 1 and 3 as unpatentable over
Ware and one of Gustavson or Ohshima but did not err in rejecting claims 5,

of the product attractive to Wilson but unrelated to the patented subject
matter.”)
6 including the requirement of claim 1 that “a third delay time [i.e., the time
from when the write command is received to when control information to
store write data is asserted internally to the memory device] is greater than
the time that transpires from when the read command is received to when
control information to output the read data is asserted internally to the
memory device”
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7-9, 11, 18, 19, 21, 22, 24, 25, or 27 as unpatentable over Ware and one of
Gustavson or Ohshima.

Gillingham Reference
Claim 14 recites that a write delay time matches the read delay time
minus a channel turnaround time. Claims 2, 6, 20, 23, and 28 recite similar
features. The Gillingham reference (U.S. Patent No. 6,008,774 – the ‘774
patent) was filed September 19, 1997 (issued July 11, 2000) and is related to
U.S. Provisional Applications 60/026,594 (September 20, 1996); 60/055,349
(August 11, 1997), and 60/057,092 (August 27, 1997). While the Examiner
states that Gillingham (the ‘774 patent) discloses a write delay time that is a
channel turnaround time less than the predetermined read delay time (RAN
10), the Examiner appears to agree that U.S. Provisional Application
60/026,594 does not disclose this feature, thus according the Gillingham
reference the priority date of August 11, 1997.
Appellant provides a Declaration by “the assignee of [the ‘953
patent]” (Declaration of Craig E. Hampel under 37 C.F.R. § 1.131, dated
September 8, 2010, ¶ 2), which states that the inventors of the ‘953 patent
“conceived of the inventions claimed in the [‘952 patent]” prior to January 2,
1997 and “continued diligently from prior to January 2, 1997 to October 10,
1997, which is the earliest filing date of [the ‘952 patent]” (Declaration of
Craig E. Hampel under 37 C.F.R. § 1.131, filed April 2, 2010, ¶ 14). The
Examiner appears to agree with Appellant, however, regarding claims 2, 6,
14, 20, 23, and 28 (which recite a write delay time matches a read delay time
minus a channel turnaround time, or similar feature), the Examiner states
that “there is [not] enough evidence, in the Davis email to establish that 8
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cycles plus the number of cycles added to the read latency matches the read
delay time minus a channel turnaround time” (RAN 26, citing Davis email)
– Exhibit CA).
We disagree with the Examiner for at least the reasons set forth by
Appellant (App. Br. 30-32). As Appellant points out, the Davis email
appears to show the disputed claimed feature at least with the specific
example described in the Davis email of a write delay time of 8 cycles being
equal to a read delay time of 9 cycles minus a channel turnaround time of 1
cycle (see, e.g., App. Br. 29-31).
The Examiner erred in rejecting claims 2, 6, 14, 20, 23, or 28 as
unpatentable over Gillingham and any one of Ohshima or Ryan.

JEDEC Reference
Claim 4 recites a third set of pins that receive a ground potential
voltage and are non-connected with respect to bond pads included on the
integrated circuit memory device. Examiner states that JEDEC provides this
feature while Appellant argues that JEDEC does not (App. Br. 26). We
agree with Appellant.
We agree with the Examiner that JEDEC illustrates a “VSS” pin (Fig.
3.11.2-1), which is a “ground reference” (p. 2-6), and an “NC” pin (Fig.
3.11.2-1), which is a pin with “no connection” (p. 2-4). However, while the
Examiner indicates that JEDEC discloses a pin that receives a ground
potential and another (separate) pin that that is not connected, the Examiner
has not demonstrated that JEDEC also discloses or suggests a pin that both
receives a ground potential and is non-connected.
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Claim 10 recites a similar feature as claim 4. Examiner does not state
that Ware, Gustavson, or Thurston provides this feature.
The Examiner erred in rejecting claims 4 and 10 as unpatentable over
JEDEC, Gustavson and one of Ware or Thurston.

CONCLUSION
The Examiner erred in rejecting claims 2, 6, 14, 20, 23, and 28 as
unpatentable over Gillingham and one of Ryan or Ohshima; claims 1 and 3
as unpatentable over Ware and any one of Gustavson or Ohshima; and
claims 4 and 10 as unpatentable over JEDEC, Gustavson and any one of
Thurston or Ware.
The Examiner did not err in rejecting claims 13, 15-17, and 26 as
anticipated by Ware; claims 5, 7-9, 11, 18, 19, 21, 22, 24, 25, and 27 as
unpatentable over Ware and Gustavson; and claims 5, 7-9, 11, 18, 19, 21,
22, 25, or 27 as unpatentable over Ware and Ohshima.

DECISION
The Examiner’s decision to reject claims 2, 6, 14, 20, 23, and 28 as
unpatentable over Gillingham and Ryan; claims 20 and 28 as unpatentable
over Gillingham and Ohshima; claims 1 and 3 as unpatentable over Ware
and any one of Gustavson or Ohshima; and claims 4 and 10 as unpatentable
over JEDEC, Gustavson and any one of Thurston or Ware is reversed.
The Examiner’s decision to reject claims 13, 15-17, and 26 as
anticipated by Ware; claims 5, 7-9, 11, 18, 19, 21, 22, 24, 25, and 27 as
unpatentable over Ware and Gustavson; and claims 5, 7-9, 11, 18, 19, 21,
22, 25, or 27 as unpatentable over Ware and Ohshima is affirmed.
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Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.

AFFIRMED-IN-PART

PATENT OWNER

STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, NW
WASHINGTON, DC 20005

THIRD PARTY REQUESTER

DAVID M. O’DELL
HAYNES AND BOONE, LLP
IP SECTION
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219