Ex Parte 7287109 et al

Board of Patent Appeals and Interferences

Mar 21, 2012

95001166 (B.P.A.I. Mar. 21, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,166 04/03/2009 7287109 2805.003REX8 7774
22852 7590 03/22/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
03/22/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Inter Partes
RAMBUS, INC.
Patent Owner
v.

NVIDIA CORP.
Requestor
____________

Appeal 2011-005255
Reexamination Control No. 95/001,166
United States Patent 7,287,1091
Technology Center 3900
____________

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON REQUEST FOR REHEARING

1 Barth et al., Method of Controlling a Memory Device Having a Memory
Core (Oct. 23, 2007).
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STATEMENT OF THE CASE
Appellant, Patent owner Rambus, filed a Request for Rehearing (see
37 C.F.R. § 41.79) seeking relief from the Decision of the Board of Patent
Appeals and Interferences affirming the Examiner’s decision to reject claims
1-25 of the ‘109 patent.2 Appellant’s sought-after relief requests a
modification of our Decision to designate it as a new ground of rejection
(see 37 C.F.R. §41.50(b)(1)) for further proceedings before the Examiner.
Third party Requestor, Respondent NVIDIA Corporation, filed Third Party
Comments on Patent Owner’s Request for Rehearing urging the Board to
deny Rambus’s sought-after relief.3
We deny the request for relief for the reasons that follow.
Exemplary Claim
Exemplary claim 1 of the ‘109 patent under reexamination follows:
1. A method of controlling a memory device having a memory core,
wherein the method comprises:

2 Decided September 1, 2011 after hearing on May 4, 2011.
3 NVIDIA has subsequently withdrawn from the appeal and seeks to
withdraw the “Comments” and its “respondent brief and supporting papers.”
See Notice of Withdrawal of Third-Party Requestor’s Appeal and Other
Papers (Feb. 17, 2012). NVIDIA does not direct the Board’s attention to
authority for withdrawing any of these papers and the request is hereby
denied. Removing references to NVIDIA’s briefs or other papers in our
prior Decision would waste resources and run counter to the “special
dispatch” mandate specifying the conduct of inter partes proceedings under
35 U.S.C. §314 (c). NVIDIA’s “Comments” is referenced below primarily
to simplify or highlight issues but it is not required to support this Decision
on Request for Rehearing.
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providing control information to the memory device, wherein the
control information includes a first code which specifies that a write
operation be initiated in the memory device;
providing a signal to the memory device, wherein the signal indicates
when the memory device is to begin sampling write data, wherein the write
data is stored in the memory core during the write operation;
providing a first bit of the write data to the memory device during an
even phase of a clock signal; and
providing a second bit of the write data to the memory device during
an odd phase of the clock signal.
Factual Findings
The Decision lists the following facts related to two embodiments,
including a “delay value” embodiment, disclosed in the ‘109 patent under
reexamination and at issue here:
The ‘109 Patent . . .
D1. The ‘109 patent discloses at least two embodiments
for operating a DRAM (dynamic random access array) memory
device. (Col. 1, ll. 20-23; col. 9, l. 26 to col. 10, l. 67.) The
disclosed DRAM comprises control logic, a clock, a receiver,
transmitter, DRAM memory core arrays, and caches. (See Fig.
6.) The first embodiment employs a strobe signal, the second
does not. In both embodiments, a memory device (e.g., a
DRAM) receives command control information causing it to
begin a process for reading data from, or writing data to, the
memory core. (Col. 9, l. 26 to col. 10, l. 67.)
. . . .
D3. In [the delay value] “alternate” embodiment,
described under a section heading titled “Decoupled Data
Transfer Control Information” (109 patent, col. 10, l.25), a
controller varies the timing of data transmission without use of
the above-described strobe signal:
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According to an alternate embodiment of the
invention, the amount of time that elapses between
the transmission of a request packet and the
transmission of the data specified in a request
packet is varied without the use of strobe and
terminate signals.
In this embodiment, the reset [sic: request]
packet contains a delay value that indicates to the
DRAM when the data specified in the request
packet will begin to be sent relative to the time at
which the request packet is sent. The DRAM
would include a counter to count the clock cycles
that elapse from the arrival of the request packet in
order to send or receive the data specified in the
request on the appropriate clock cycle. Because
the controller may vary the latency between the
request packet and the data transmission, the
controller is able to dynamically adjust the
operative interleave on the channel . . . .
(Col. 10, ll. 52-67.)

D4. According to the ‘109 patent, in contrast to the two
embodiments discussed supra, prior art systems control the data
transfer timing based on a fixed number of clock cycles after
the clock cycle on which a request packet arrives. As such,
these “prior art systems [are] inflexible with respect to how
control and data signals may be interleaved” (col. 10, ll. 37-39)
because the timing delay value in such prior art systems is fixed
in a register within a DRAM. (See col. 10, ll. 28-67.)

(Decision 2-5.)

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The Decision also lists the following facts related to a similar “delay
value” embodiment in the prior art Farmwald patent (also assigned to patent
owner Rambus):4
Farmwald
F1. Farmwald discloses using request packets which can
vary the data block transfer time in manner which is similar to
the alternate (delay value/non-strobe) embodiment of the ‘109
patent (D3), to determine when to read or write data from a
memory device:
The data block transfer occurs later at a time
specified in the request packet control information,
preferably beginning on an even cycle. A device
begins a data block transfer almost immediately
with a device-internal phase as the device initiates
certain functions, such as setting up memory
addressing, before the bus access phase begins.
The time after which a data block is driven onto
the bus lines is selected from values stored in slave
access-time registers. The timing of data for reads
and writes is preferably the same; the only
difference is which device drives the bus.
(Col. 9, ll. 18-30.)
. . . .
F3. More specifically, the data transfer timing
information arrives in the request packet in the form of an “op
code,” and this particular op code can either be used to select a
certain register in the slave DRAM memory device which
stores the (delay value) timing information, or the op code can
indirectly indicate pre-selected (delay value) access times.
(Col. 9, l. 46 to col. 10, l. 5.)

4 Farmwald et al. U.S. 6,584,037 B2 (June 24, 2003) - also referred to as
“Farmwald ‘037” elsewhere in these proceedings.
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F4. With further respect to this delay value, Farmwald
dependent claim 28 recites “outputting a value to the memory
device, wherein the value is representative of the delay time;
and outputting a second operation to the memory device,
wherein the second operation code instructs the memory device
to internally store the value.”

(Decision 6-7.)
ANALYSIS
Rambus contends that the Board committed procedural error by
failing to designate a new ground of rejection after allegedly finding new
facts not found by the Examiner. (See Rehearing Req. 2-6.) This contention
lacks merit.
The Decision focuses on claim interpretation; in particular, whether
or not the recited “signal” in claim 1 embraces a “delay value” signal as
disclosed in the prior patent to Farmwald. (See, e.g., Decision 10-11, supra
D1, D3, D4, F1, F3, F4.) Of course, the resolution of this central issue
necessarily involves the ‘109 patent under reexamination. Claim
interpretation is a matter of law, but claims “must be read in view of the
specification.” Phillips v. AWH Corp., 415 F.3d, 1303, 1315 (Fed. Circ.
2005) (citation omitted) (en banc).
Rambus agrees that the central issue on appeal involves interpreting
the scope of the claimed signal: “Appellant [Rambus] frames the central
anticipation issue on appeal as ‘whether the storing of a value in an access-
time register as described in [Farmwald] anticipates or renders patentably
indistinct the providing a signal step in the ‘109 patent.’ (App. Br. 12.)”
(Decision 9 (internal quotations omitted, quoting Rambus’s Appeal Brief).)
And as NVIDIA explains, “[t]he Decision’s comparison of the claimed
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‘signal’ with Farmwald’s ‘delay value’ is the very same comparison made
by the Examiner during the reexamination prosecution.” (Comments 2.)
Farmwald and the ‘109 patent under reexamination are both assigned
to Rambus and describe similar inventions. Both include a “delay value”
signal embodiment according to our Decision, the Examiner’s findings,
Rambus’s arguments, and Micron’s contentions. (Compare Decision D1,
D3, D4 with F1, F3, F4) (listed supra and discussing the delay value signal
embodiments in the respective patents); accord App. Br. 12, 19-20; RAN
10; Req. Resp. Br. 2-3, 5, 8.)
To determine the meaning and scope of the claimed signal, the
Decision compares the delay value signals in the ‘109 patent and Farmwald
based on the Examiner’s findings of similarity between the two:
The Examiner relies on similarities between Farmwald’s
programmable delay value (see F1-F4) and the ‘109 patent’s
non-strobe delay value embodiment (D3) to show anticipation:

the disclosed [109’ patent’s] “delay value” is
characterized as a signal since it [sic] [is] provided
to the memory device for signaling the memory
device to perform a specific function. In this case
the delay value signal indicates that the memory
device should wait a certain amount of clock
cycles before outputting data. This signal is the
same as disclosed by . . . Farmwald. That is, the
number of clock cycles to wait before data is
sampled is received from a controller as a value.
(RAN 10.)

The arguments and findings of record show that there are
no material factual disputes about the delay value systems in
Farmwald or the ‘109 patent – i.e., the disputes turn on claim
interpretation. That is, Farmwald, in a manner similar to the
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‘109 patent, discloses a controller which provides separate
instructions/codes in a request packet – (at least) 1) one for
designating a read or write operation, and 2) another for
designating a delay value. (Compare F1-F5 with D3-D4.)

(Decision 10-11 (emphasis added).)
The Decision further examines the scope of the claimed signal,
relying on the ‘109 patent and similarities to Farmwald, as follows:
Based on the ‘109 patent and the generic claim language,
skilled artisans reasonably would have considered “providing a
signal” as transmitting or otherwise providing additional control
information (i.e., additional to a first code) within a request
packet, such as the variable delay value signal. Alternatively,
skilled artisans would have considered either 1) storing the
delay value in the access-register, 2) retrieving it, or 3)
comparing it to a clock value and generating another (implicit)
signal, as Farmwald provides, as also constituting “providing a
signal,” as recited in claim 1. Under any of these latter
alternatives, Farmwald’s delay value signal, as provided at
these latter stages in the memory device, is provided separately
from the “control information” provided in the request packet.
(Decision 13-14.)

As these passages show, the central thrust of the Decision tracks the
Examiner’s reliance on Farmwald’s delay value signal which includes the
four options listed supra (i.e., the request packet delay value signal option
plus the three other numbered options listed in the passage supra). Rambus
asserts that these four delay value options constitute new factual findings.
(See Rehearing Req. 3-4 (listing four allegedly new options in the
Decision).)
Rambus bases this assertion on the Examiner’s finding that claim 28
of Farmwald reads on the claimed signal. Claim 28 recites “outputting a
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value to the memory device, wherein the value is representative of the delay
time.” (Rehearing Req. 3 (citing RAN at 16-17).) According to Rambus,
the four listed options, which Rambus does not dispute are disclosed in the
‘109 patent or Farmwald and any one of which shows anticipation, are “not
the same as” the delay value recited in claim 28 of Farmwald. (Rehearing
Reg. 3-4.)
Rambus’s assertion lacks merit. The Examiner relied on more than
just claim 28 of Farmwald as discussed further below. (See e.g., Comments
3 (listing “delay value” RAN cites showing Examiner findings related to the
four options).) These four options simply catalogue different ways the delay
value in Farmwald and the ‘109 patent corresponds to the claimed signal
based on findings by the Examiner. (See Comments 2-3 (listing RAN 9-12,
14, 16-18, 45, 49, 54, 59 as supporting the Board’s claim interpretation
reading “signal”on Farmwald’s delay value signal).) For example, 1) the
value comes from a request packet; 2) the value is stored in an access
register; 3) the value is provided for comparison to a clock; and/or 4) the
value is used to generate another signal after a match with the clock.
With respect to allegedly new option 1, Rambus previously argued
that a value in a packet cannot be a signal. (See RAN 10 (discussing
Rambus’s arguments (citing ‘109 patent, col. 10, ll. 52-56).) The Examiner
ultimately disagreed with Rambus, finding the “delay value signal” to be
“the same as disclosed by ‘037 Farmwald” with the value received by a
controller (i.e., implying a packet sent by the controller). (See RAN 10.)
Thus, option 1 does not constitute a new fact or issue. And in any event,
Rambus cannot claim surprise over the fact that its Farmwald and
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‘109 patents disclose a packet with a signal (i.e., a delay value). (See F3,
D3.)
With respect to allegedly new option 2, Rambus specifically referred
to it as “the crux of the dispute,” framing the issue as “whether the storing of
a value in an access-time register as described in [Farmwald] anticipates or
renders patentably indistinct the providing a signal step in the ‘109 patent.”
(App. Br. 12. (emphasis added).) Certainly, the crux of the dispute and an
admission that Farmwald stores a delay value in an access time register
cannot constitute a new factual issue. And as NVIDIA indicates
(Comments 3 (citing RAN)), the Examiner similarly found that the delay
value is programmable and stored in an access register. (Accord RAN 12,
14, 16, 28, 45, 49, 54, 59).)
With respect to options 3 and 4, Rambus argued in its Appeal Brief
that “passively waiting for a number of clock cycles to expire” cannot
constitute the claimed signal. (App. Br. 12.) This argument corresponds to
options 3 and 4 which simply explain how the delay value constitutes a
signal: i.e., 3) the memory device compares the delay value number
(a signal) to a clock, or 4) a new signal (a trigger) is created to indicate the
delay value number and external clock match. In other words, these claim
interpretation options respond to Rambus’s argument and show how
passively waiting for a clock value thereafter corresponds to the claimed
signal. The Examiner similarly addresses this passive waiting and also
implies comparing the delay value to an external clock by describing the
delay value number as a programmable “trigger.” (RAN 9, 11, 12; accord
Comments 3.)
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With further respect to this same “delay value,” signal in both patents,
Rambus contends that by addressing Rambus’s assertions that “inflexible”
prior art systems (see supra D4) fall outside the claimed signal, the Decision
found new facts. (Rehearing Req. 4-6.) But as NVIDIA implies, our
Decision merely addresses Rambus’s arguments and compares the
‘109 patent’s discussion of “inflexible” prior art systems to Farmwald’s
delay value embodiment to determine if the latter is “inflexible” in the
context of the ‘109 patent. (See Comments 3.)
In other words, the Decision maintains the Examiner’s reliance on the
same delay value signals in the ‘109 patent and in Farmwald as the
following passage shows:
In further attempting to show that Farmwald does not
anticipate claim 1, Appellant [Rambus] states that “the
‘037 patent [i.e., Farmwald] discloses a type of prior art system
that the ‘109 patent describes as ‘inflexible’.” (App. Br. 11,
accord App. Br. 23.) This argument improperly characterizes
the Farmwald system and fails to recognize that it is similar to
the ‘109 patent’s delay value embodiment. (Compare F1-F4
with D3.)
According to the ‘109 patent, the prior art “inflexible”
systems provide a fixed (stored) latency and preclude data and
control interleaving on the data bus. In contrast, the delay value
(non-strobe) embodiment allows the controller to “vary the
latency between the request packet and the data transmission,
[and] the controller is able to dynamically adjust the operative
interleave on the channel.” (D3.) This delay value embodiment
is described in a section titled “Decoupled Data Transfer
Control Information,” implying one reason (i.e., decoupling) for
its flexibility. (D3.) Hence, the ‘109 delay value embodiment
is not “inflexible.”
And similar to the ‘109 patent’s delay value embodiment,
Farmwald’s delay value system provides similar flexibility;
i.e., more than the inflexible prior art systems - by allowing the
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delay value to be varied by the controller, for example, by
sending a request packet having a code for selecting different
access-time registers each storing a different delay value, by
otherwise programming and storing different values in such
access-time registers, or by sending different operation codes
representing different delay values. (See F1-F4 and Appellant’s
arguments describing Farmwald as discussed supra.)
(Decision 14-15.)
As the passage shows, the thrust of the Decision never deviates from
the Examiner’s central finding that Farmwald’s delay value embodiment
satisfies the signal recited in claim 1 based on a similar embodiment in the
‘109 patent. In other words, Rambus’s reliance on In re Leithem, 661 F.3d
1316 (Fed. Cir. 2011) (discussing new ground) is misplaced. (Compare
Rehearing Req. 2-3 (citing)) with Comments 3-4 (distinguishing Leithem).)
Following Phillips, the Decision focuses on what the ‘109 patent
means by and embraces with the disputed claim term “signal” and responds
to Rambus’s claim interpretation theory, which amounts to a disavowal
theory based on disparaged (i.e., “inflexible”) prior art. The Examiner
implicitly disputed Rambus’s disavowal claim theory by maintaining
throughout the reexamination proceedings that claim 1 embraces the delay
value signals in both patents. (See RAN 10 (finding that “the disclosed
‘delay value’ is characterized as a signal” and “[t]his signal is the same as
disclosed by ‘037 Farmwald).)
As discussed above, the Examiner finds that Farmwald’s delay value
is programmable and stored in an access register. The Examiner also finds
that Farmwald’s memory device receives “the number [i.e., the delay value]
of clock cycles . . . from a controller as a value.” (RAN 10.) And as Rambus
notes, the Examiner also finds that Farmwald teaches “outputting a value to
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the memory device, wherein the value is representative of the delay time.”
(Rehearing Req. 3 (citing RAN at 16-17).) These findings coalesce with the
Board’s claim interpretation and show that the Examiner implicitly found
that Farmwald’s delay value embodiment is not inflexible; i.e., since the
delay value can be programmed by the controller, Farmwald’s system
flexibly has the ability to vary the timing between control signals and data
writes and reads. (See D3, D4 (discussing and contrasting flexible and
inflexible systems).)
In any event, to determine the claim scope, under Phillips, the Board
had to consider, in its Decision, Rambus’s disavowal claim theory based on
“inflexible” prior art systems, filling in any gaps pursuant to Rambus’s
citations to the ‘109 patent describing these inflexible systems. (See App.
Br. 8, 11, 20 (citing the ‘109 patent at col. 10, ll. 52-56 describing
“inflexible” prior art systems.).) Prior to the Decision, Rambus pointedly
did not argue in its Appeal Brief that the Examiner failed to consider
Rambus’s disavowal claim theory based on these “inflexible” prior art
systems. And Rambus was free to supplement its Appeal Brief claim
interpretation theory which Rambus seeks to do now, to try to show that
prior art systems (including delay value systems) are “inflexible” according
to the ‘109 patent. Rambus also could have requested the Board to remand
this disavowal theory back to the Examiner to consider it (i.e., before the
Board’s Decision).
In other words, Rambus had several options. But it chose the option
of inviting the Board to consider its disavowal theory, however sparse it may
have been presented, based on the ‘109 patent’s column 10 discussion of
“inflexible” prior art systems. (See App. Br. 20 (citing the ‘109 Patent at
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col. 10, ll. 52-56 for consideration).) Rambus now complains because the
Board did exactly what Rambus invited it to do – consider the ‘109 patent at
column 10 to interpret whether that passage precludes reading the claim 1
“signal” on prior art “delay value” signals.
Procedurally, Rambus cannot now declare surprise based on limited
facts Rambus directed the Board to consider at column 10 in the ‘109 patent,
especially here, when those facts, at most, merely fill in the gaps in support
of a claim interpretation which Rambus has argued, throughout these
proceedings, to be improper. The Examiner, Respondent, Rambus, and the
Board each focus on the delay value signal embodiments in the ‘109 patent
and Farmwald. The Decision simply determines that the ‘109 patent’s delay
value embodiment (also described at column 10 of the ‘109 patent (see D3,
D4)) supports the Examiner’s claim interpretation under which the claimed
signal reads on Farmwald’s similar delay value embodiment.
Substantively, Rambus’s new arguments and proffered evidence (see
Rehearing Req. 5 (citing, inter alia, “ITC” findings)) fail to show error in
the Decision. As the Decision shows, column 10 of the 109’ patent
(to which Rambus directed the Board to consider Rambus’s disavowal
theory) includes a section entitled “Decoupled Data Transfer Control
Information” which describes the “delay value” embodiment in dispute.
(See Decision 4; supra D3.) That section, as the Decision indicates,
unequivocally shows that the “decoupled” delay value embodiment “may
vary the latency,” “dynamically adjust . . . interleave,” and vary “the amount
of time that elapses between the transmission of a request packet and the
transmission of the data.” (D3.) Rambus’s Appeal Brief highlights this
“contrast” over inflexible prior art systems by pointing out that in the ‘109
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patent, “control timing is decoupled from data timing.” (App. Br. 8
(emphasis added).)
In other words, contrary to Rambus’s arguments, as the Examiner at
least implicitly found as discussed supra, the similar delay value
embodiments in the ‘109 patent and Farmwald are not inflexible. As the
Examiner explicitly found, both embodiments are within the scope of the
claimed signal. (See also Decision 14-15 (discussion quoted supra); D3,
D4, F3, F4.) Rambus’s Rehearing Request fails to show procedural or
substantive error in the Examiner’s claim interpretation adopted in the
Decision.
The voluminous record before the Board includes at least 4,817 pages
and indicates that Rambus has had fair opportunity to be heard on claim
interpretation and a wide array of procedural and substantive matters. The
Examiner made myriad findings and responses as summarized in an 84 page
RAN (and other prior office actions). Rambus’s complaints here alleging
unfair surprise and a denial of a fair opportunity to be heard “attempt[] to
make a mountain out of a mole-hill.” See Application of Bush, 296 F.2d 491,
96 (CCPA 1961).
Based on the foregoing discussion, Rambus has not shown procedural
error in our Decision.
DECISION
We decline to designate our Decision as a new ground of rejection.
Appellant’s sought-after relief is
DENIED

ak
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Finnegan, Henderson, Farabow, Garrett & Dunner LLP
901 New York Ave., N.W.
Washington, DC 20001

Third Party Requester:

Haynes and Boone, LLP
2323 Victory Avenue
Suite 700
Dallas, TX 75219