Ex Parte 6,715,020 et al

Patent Trial and Appeal Board

Feb 14, 2014

95001472 (P.T.A.B. Feb. 14, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,472 10/20/2010 6,715,020 42940.27 4483
86497 7590 02/14/2014
Paul M. Anderson, PLLC
P.O. Box 160006
Austin, TX 78716
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
02/14/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

NVIDIA CORPORATION
Requester

v.

RAMBUS INC.
Patent Owner

____________________

Appeal 2012-012567
Inter partes Reexamination Control No. 95/001,472
Patent 6,715,020 B2
Technology Center 3900
____________________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

SIU, Administrative Patent Judge.

DECISION ON REQUEST FOR REHEARING
In papers filed August 16, 2013, Patent Owner requests a rehearing
under 37 C.F.R. § 41.79 from the Decision on Appeal of the Patent Trial and
Appeal Board, dated July 16, 2013. In the Decision, we affirmed the
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Examiner’s rejection of claims 1, 2, 5, 13, 38, 41, 44, and 47 as unpatentable
over the combination of Baror
1
and iRAM
2
(Decision 10).
Patent Owner re-iterates that “the Examiner recognized . . . [that]
Baror does not disclose DRAM” (Req. Reh’g 2; see also PO App. Br. 2, “the
Examiner correctly recognizes that Baror does not disclose a DRAM”). As
an initial matter, we note that the Examiner actually stated that Baror “does
not specifically disclose what type of random access memory is used” (Ans.
32) and does not find that Baror “does not disclose a DRAM,” as Patent
Owner contends. Hence, the Examiner actually finds that Baror discloses
the use of a random access memory and that iRAM discloses that one of
ordinary skill in the art would have understood the benefits of using a
DRAM as a random access memory. Such benefits include, according to the
Examiner, “high capacity, moderate speeds and low power consumption” or
“large amounts of memory at the lowest cost per bit” (Ans. 32-33). The
Examiner further explained that “using well known DRAM cells for Baror’s
memory is merely the combination of familiar elements according to known
methods that does no more than yield predictable results” (Ans. 33). As the
Decision explains, we agree that the Examiner explained how each claim
limitation is disclosed or suggested by the combination of Baror and iRAM
and articulated sufficient reasoning with rational underpinning to justify
support for the conclusion of obviousness (see e.g., Ans. 30-41).

1
U.S. Patent No. 5,025,366.
2
Intel Corporation, Memory Components Handbook, Chapter 1 and Chapter
3, Application Note AP-132, 1982/1985 (“iRAM”).
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Patent Owner argues that the Examiner fails to “support using DRAM
in the integrated cache unit [of Baror] or any reason why one of ordinary
skill in the art would do so” (Req. Reh’g 3). As previously discussed,
however, the Examiner finds that it would have been obvious to one of
ordinary skill in the art to use the DRAM (e.g, as disclosed by iRAM) as a
random access memory in Baror because, according to the Examiner, one of
ordinary skill in the art would have understood, among other things, that
doing so would have provided “high capacity, moderate speeds and low
power consumption” or “large amounts of memory at the lowest cost per
bit” (Ans. 32-33). Hence, we disagree with Patent Owner’s contention that
the Examiner fails to support using DRAM in the system of Baror.
Patent Owner argues that “Baror requires . . . cache units to operate as
high speed caches that provide faster access to data” and suggests that the
DRAM of iRAM does not provide sufficiently “high” speed for the alleged
need for “high speed” of Baror. (Req. Reh’g 4). Patent Owner further cited
to the Murphy Declaration (at ¶ 27) and the Supplemental Murphy
Declaration (at ¶¶ 5-8) as support for the contention that the “moderate
speed” DRAM of iRAM was too slow to operate in a circuit of Baror that
allegedly required “higher speed.” For example, Patent Owner’s declarant
(i.e., Mr. Murphy) alleges that “the limited speed of DRAM devices is not
compatible with the . . . high speed processing operations [of Baror]” (Suppl.
Murphy Decl. ¶ 6).
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This argument was previously addressed in the Decision (see e.g.,
Decision 3-9). For example, Patent Owner and Patent Owner’s declarant do
not define how fast a circuit would need to operate to be considered “high
speed” by one of ordinary skill in the art. Patent Owner argued previously,
however, that the circuit of Baror “requires higher performance than the
‘moderate speed’ of DRAMs” (PO App. Br. 3), implying that whatever the
level of performance necessary to be deemed “high speed” by one of
ordinary skill in the art must be higher than “moderate speed,” as disclosed
by iRAM. However, as we previously pointed out, Patent Owner provides
insufficient evidence to support its argument that the disclosure of iRAM
with alleged subjective “moderate speed” (the speed of which is unspecified
by iRAM) was too slow to operate in the system of Baror that allegedly
requires a subjectively “higher” speed (the speed of which is unspecified by
Baror). Patent Owner does not point to any specific values of speed to
demonstrate persuasively that the “moderate speed” of iRAM is, in fact, less
than what the Patent Owner implied was “higher speed” used in Baror as to
be incompatible with or inoperable in the system of Baror.
Nor does Mr. Murphy’s statement that “the limited speed of DRAM
devices is not compatible with the . . . high speed processing operations [of
Baror]” (Suppl. Murphy Decl. ¶ 6) provide sufficient detail to ascertain what
speed one of ordinary skill in the art would have considered “high” speed
and whether the speed of DRAM devices would be insufficient to operate at
that alleged “high” speed. Mr. Murphy’s statement also does not sufficiently
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indicate the specific speed of the DRAM of iRAM. Thus, Mr. Murphy
provides insufficient information and evidence to demonstrate that the
DRAM of iRAM (as opposed to “DRAM devices” in general) is “low
speed,” or “lower” (i.e., “moderate”) than the subjective “higher” speed of
Baror. Mr. Murphy also provides insufficient information and evidence to
demonstrate that the alleged “lower” (or “moderate”) speed of iRAM’s
DRAM (assuming that the speed of iRAM’s DRAM is, in fact, “lower” than
some unspecified value corresponding to alleged “higher” speeds that Patent
Owner ascribes to the Baror system) is sufficiently “lower” so that one of
ordinary skill in the art would have been dissuaded from combining the
Baror and iRAM references, despite potential “high capacity, moderate
speeds and low power consumption” or “large amounts of memory at the
lowest cost per bit” (Ans. 32-33). For similar reasons, we are also not
persuaded by Mr. Murphy’s additional statement in the Murphy Declaration
that the “limited speed of DRAM devices” is insufficient “for high speed”
processes (Murphy Decl. ¶ 27). We agree with the Examiner and Requester
that Mr. Murphy’s statement is insufficient to refute the Examiner’s prima
facie showing of obviousness.
Mr. Murphy also states that “DRAMs . . . typically make up main
memory [and] are not suitable for high speed caches” and that “static
RAM . . . is commonly used for cache structures” (Murphy Decl. ¶ 27). As
an initial matter, Mr. Murphy merely states that the use of DRAMs in main
memory is “typical” and that the use of static RAM for cache structures is
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“common.” Mr. Murphy does not provide sufficient evidence to
demonstrate or even assert, however, that DRAMs are always used in main
memory and never used in cache structures (or that static RAMs are used
exclusively and to the complete exclusion of DRAMs in cache structures).
Also, even assuming that Mr. Murphy is correct that DRAMs are
“typically” used in main memory and that static RAMs are “commonly”
used in cache structures, Mr. Murphy’s observations do not shed light on
whether (or not) it would have been obvious to one of ordinary skill in the
art to have combined the iRAM and Baror references. Nor do Mr. Murphy’s
statements of what type of RAM is “commonly” or “typically” used
sufficiently demonstrate that, in fact, using the DRAM of iRAM in the
system of Baror would be undesirable to one of ordinary skill in the art or
inoperable in the system of Baror, for example. As previously discussed,
Mr. Murphy’s allegations do not refute the Examiner’s findings that one of
ordinary skill in the art would have understood that using the DRAM of
iRAM in Baror would have resulted in “high capacity, moderate speeds and
low power consumption” or “large amounts of memory at the lowest cost
per bit” (Ans. 32-33).
Mr. Murphy further asserts that Baror discloses a circuit used “in
Reduced Instruction Set Computer (RISC) processing systems” and that Mr.
Murphy was “aware that Advanced Micro Devices (AMD) produced such
systems . . . [that] included SRAM memory cells, and not DRAM cells”
(Supp. Murphy Decl. ¶ 7). First, we note that Mr. Murphy does not specify
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whether Baror uses DRAM or SRAM. Instead, Mr. Murphy merely asserts
that he is aware that AMD produced certain systems that included SRAM
memory cells instead of DRAM cells. Mr. Murphy does not assert or
demonstrate that AMD did not produce any systems that used DRAM cells
or that the system produced by AMD that contained “SRAM memory cells,
and not DRAM cells” was the only system produced by AMD. Nor does
Mr. Murphy indicate that the system disclosed by Baror is the same system
that Mr. Murphy is “aware” that “included SRAM memory cell, and not
DRAM cells.” Mr. Murphy’s statement that AMD produced certain systems
that “included SRAM memory cells, and not DRAM cells” is insufficient to
demonstrate that AMD did not produce or consider any other systems that
included DRAM cells and that the system described in Baror is the system of
which Mr. Murphy is aware (i.e., a system that “included SRAM memory
cells, and not DRAM cells”). Therefore, we agree with the Examiner that
Mr. Murphy’s statement is insufficient to demonstrate that Baror’s “random
access memory” must be SRAM and cannot be DRAM, as Patent Owner
alleges.
In any event, Mr. Murphy’s statement does not address whether it
would have been obvious (or not) to one of ordinary skill in the art to have
combined the iRAM and Baror references. As previously stated, the
Examiner finds that one of ordinary skill in the art would have understood
that using the DRAM of iRAM in the Baror system would have resulted in
“high capacity, moderate speeds and low power consumption” or “large
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amounts of memory at the lowest cost per bit” (Ans. 32-33) and that,
therefore, it would have been obvious to one of ordinary skill in the art to
have combined the references. Even assuming that Baror uses SRAM and
not DRAM, the Examiner relies on the combination of iRAM (that discloses
DRAM) with Baror. Mr. Murphy’s statement merely indicates that Mr.
Murphy is aware that AMD produced certain systems that used SRAM but
not DRAM. This allegation of awareness, even if true, is insufficient to
refute the Examiner’s prima facie showing of obviousness.
Mr. Murphy also states that Baror discloses “high-speed RISC
processing systems” that can include multiple processors (Supp. Murphy
Decl. 8, citing Baror at col. 1, ll. 16-18, 34-38) and that, according to Mr.
Murphy, one of ordinary skill in the art would have understood that RISC
processors . . . would not have used disk memory as ‘main memory’” (id.).
Mr. Murphy appears to assert that Baror discloses a “RISC processing
system” and that it would not have been obvious to one of ordinary skill in
the art to have used a DRAM (e.g., of iRAM) in a RISC processing system
(of Baror).
Even assuming to be correct Mr. Murphy’s statement that one of
ordinary skill in the art would supposedly “not have used disk memory as
‘main memory’,” and that in so doing, it would not have been obvious to one
of ordinary skill in the art to combine the teachings of iRAM (e.g., DRAM)
with a RISC processing system (of Baror), as discussed in the Decision,
Baror discloses “implement[ing] cache function in . . . [a] non-RISC
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environment” (Decision 4, citing Baror at col. 2, ll. 1-2). While Mr. Murphy
alleges that with the use of RISC processors, one of ordinary skill in the art
would not have used disk memory as main memory (and that, allegedly, it
would not have been obvious to one of ordinary skill in the art to have used
a DRAM (of iRAM) in a RISC processing system), Mr. Murphy does not
assert and provides insufficient evidence to demonstrate that with the use of
non-RISC processors (as in an embodiment of Baror), one of ordinary skill
in the art also would “not have used disk memory as main memory.” Thus,
Patent Owner does not sufficiently refute the Examiner’s prima facie
showing that it would have been obvious to one of ordinary skill in the art to
have combined the teachings of Baror and iRAM.
Patent Owner argues that “[e]ven in a non-RISC environment, a cache
is still required to provide high speed access to data” (Req. Reh’g 7) but, as
previously discussed, does not sufficiently demonstrate how “high” the
speed must be in a cache, what the speed of a DRAM is, and if that speed (of
the DRAM) is prohibitively “lower” than the presumed “high” speed
(however “high” it is) of the cache (of Baror), and even if the speed of the
DRAM (alleged to be “moderate”) is “lower” than the “high” speed of a
cache, how the specific difference in speed (whatever the difference, if any,
might be) would affect the circuit such that one of ordinary skill in the art
would be discouraged from using the DRAM. At least in the absence of any
such evidence, we are not persuaded by Patent Owner’s generalized
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statement that even in a non-RISC environment, a cache is supposedly
required to provide “high speed” data access.
Patent Owner further argues that “[w]hile iRAM suggests the benefits
of using DRAM, it does so in the context of main memory” (Req. Reh’g 4).
Even assuming Patent Owner’s contention to be true, Patent Owner does not
demonstrate that the combination of iRAM and Baror, rather than iRAM in
isolation, also fails to disclose or suggest using DRAM in association with
the system of Baror.
Patent Owner argues that iRAM “counsels away from using DRAM
for cache structures” (Req. Reh’g 4). In support of this contention, Patent
Owner cites iRAM as disclosing “a global memory [that] is greater than 64K
bytes and serves as a main memory,” “dynamic RAMs for read/write
memory . . . to provide the highest density and lowest cost per bit,” “[w]here
large amounts of memory at the lowest cost per bit is required, such as main
computer memory, the dynamic RAM holds a commanding position” (Req.
Reh’g 4, citing iRAM at 1-5 and 3-432). While iRAM appears to disclose a
memory that is greater than 64K bytes and dynamic RAMs that provide the
highest density and lowest cost per bit, contrary to Patent Owner’s
contention, Patent Owner has not demonstrated sufficiently that one of
ordinary skill in the art, upon gaining knowledge from iRAM that memory
can be greater than 64K bytes and that dynamic RAMs provide the highest
density and lowest cost per bit, would be “counseled away from” using
DRAM. On the contrary, we agree with the Examiner that it would have
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been obvious to one of ordinary skill in the art to have used DRAM at least
because, according to iRAM, doing so would provide the highest density and
lowest cost per bit (among other stated reasons of record in iRAM).
Patent Owner argues that “[t]he Examiner did not provide any
evidence to support that DRAM would provide an interface suitable for use
in the integrated cache unit of Baror” (Req. Reh’g 5). Patent Owner does
not indicate that this argument pertaining to the DRAM interface was
previously presented in the Briefs. Arguments not raised in the briefs before
the Board and evidence not previously relied upon in the briefs are not
permitted in the request for rehearing. 37 C.F.R. § 41.79(b)(1). In any
event, as the Examiner stated and as Patent Owner does not dispute, Baror
discloses random access memory (as does iRAM). Given that one of
ordinary skill in the art would have known to use random access memory (as
disclosed by Baror and iRAM), we agree with the Examiner that it would
have been obvious to one of ordinary skill in the art to have used an interface
associated with and corresponding to the random access memory. For
example, it would have been merely a matter of common sense for one of
ordinary skill in the art to use an interface that was compatible with a
corresponding a random access memory rather than an interface that was
incompatible with a random access memory because using an incompatible
interface would have resulted in a higher risk of inoperability with the
incompatible memory. One of ordinary skill in the art would have
understood this risk of inoperability to be reduced if the interface used was
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compatible with the corresponding memory. “It is common sense that
familiar items may have obvious uses beyond their primary purposes, and a
person of ordinary skill often will be able to fit the teachings of multiple
patents together like pieces of a puzzle.” KSR Int’l Co. v. Teleflex, Inc., 550
U.S. 398, 402 (2007). In addition, the record does not show that effecting
such a combination, or using a random access memory with a corresponding
interface appropriate for the random access memory used, was “uniquely
challenging or difficult for one of ordinary skill in the art.” See Leapfrog
Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007)
(citing KSR, 550 U.S. at 418).
Patent Owner argues that Patent Owner’s declarant’s statements of the
alleged incompatibility of the DRAM of iRAM and the system of Baror is
“supported by the AMD datasheets and excerpts from the Prince book –
neither of which were acknowledge or addressed by the Board” (Req. Reh’g.
6).
In particular, Patent Owner argues that the Board overlooked “the
AMD Am29062 ‘Integrated cache unit with 8K byes RAM” (Req. Reh’g 6).
Patent Owner previously submitted evidence allegedly demonstrating that
the Baror system used only “SRAM, not DRAM” because, according to
Patent Owner, the “AMD Am29062 “integrated cache unit with 8K [bytes]
RAM” was used with the “AMD 29000 RISC CPU family,” “matches the
description of the integrated cache unit in Baror,” and “relied on SRAM, not
DRAM” (PO App. Br. 4, citing Ex. P-13 at 7; Ex. P0-14 at 1, 13).
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We have carefully considered the “AMD datasheets” but do not find
them to be sufficiently persuasive to support Patent Owner’s contention that
Baror “used only SRAM, not DRAM.” We also are not persuaded that even
if Baror used “only SRAM,” that it would not have been obvious to one of
ordinary skill in the art to have combined the teachings of iRAM with that of
Baror.
Patent Owner argues that the “AMD datasheets” merely “matches the
description of the integrated cache unit in Baror” but does not demonstrate
sufficiently or assert that the “AMD datasheets” describe the same system as
that disclosed by Baror. Thus, Patent Owner has not demonstrated
persuasively that the system of Baror used only “SRAM, not DRAM,” even
assuming that the system described by “AMD datasheets” used only
“SRAM, not DRAM.” Indeed, as discussed previously, the Examiner
established, and Patent Owner did not dispute, that Baror does not disclose
specifically the type of random access memory used while, according to
Patent Owner, “AMD datasheets” discloses using only “SRAM, not
DRAM.” This would indicate that, contrary to Patent Owner’s contention,
the “AMD datasheets” does not “match the description of the integrated
cache unit in Baror” as alleged by Patent Owner because “AMD datasheets”
allegedly specifically limits the random access memory used to “SRAM, not
DRAM” while Baror does not.
In addition, even assuming that the “AMD datasheets” describe the
exact system as that disclosed by Baror (and that Baror uses only “SRAM,
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not DRAM”), as Patent Owner implies, the “AMD datasheets” do not
adequately support Patent Owner’s apparent contention that it would not
have been obvious to one of ordinary skill in the art to have combined the
teachings of iRAM and Baror. As previously discussed and as pointed out
by the Examiner, Baror discloses a system that uses random access memory
while iRAM discloses that using DRAM as random access memory would
have resulted in, for example, “high capacity, moderate speeds and low
power consumption” and “large amounts of memory at the lowest cost per
bit” and that “using well known DRAM cells for Baror’s memory is merely
the combination of familiar elements according to known methods that does
no more than yield predictable results” (Ans. 32-33). Patent Owner does not
indicate specific disclosures in the “AMD datasheets” that adequately refute
the Examiner’s prima facie showing of obviousness. In summary, we have
carefully considered the “AMD datasheets” but are not persuaded by Patent
Owner’s assertions with respect to the information provided therein.
Patent Owner argues that the Board overlooked an excerpt from “High
Performance Memories” by Betty Prince (“Prince”) (Req. Reh’g 6). Patent
Owner previously submitted “[a]n excerpt from ‘High Performance
Memories’ by Betty Prince” to allegedly demonstrate that “SRAM is used in
cache structures such as that shown in Baror” (PO App. Br. 4, citing Ex. P-
4a (“Prince”) at 6-7). According to Patent Owner, Prince discloses:
The cache subsystem is the result of the discrepancy in speed
capability and price between the SRAMs and DRAMs. This
led to a split of the main memory into a hierarchy in which a
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small fast SRAM cache is inserted in to the system between the
microprocessor and a larger bank of slower but less expensive
DRAM main memory.

(Ex. P-4a (“Prince”) at 6-7).
Hence, Patent Owner indicates that Prince discloses the use of “small
fast SRAM cache” inserted between a microprocessor and DRAM main
memory. Patent Owner does not demonstrate sufficiently that Prince also
discourages one of ordinary skill in the art to combine the teachings of
iRAM with those of Baror. Prince merely discloses that a “small fast SRAM
cache” may be inserted between a microprocessor and DRAM main memory
but Patent Owner does not demonstrate adequately that Prince also, for
example, disparages (or even comments on) incorporating a DRAM in the
Baror system. Therefore, after careful consideration of the Prince reference,
we remain unpersuaded by Patent Owner’s arguments.
Patent Owner argues that “Rambus presented evidence that Burst
EDO and ‘High Speed Toggle’ – asynchronous memory device that were
developed in an attempt to address the memory bottleneck – . . . [were] not
commercially successful” (Req. Reh’g. 8, citing PO App. Br. 15 and
Murphy Decl. at ¶ 13) and that “[t]he Board should not dismiss Rambus’s
compelling evidence of commercial success” (Req. Reh’g. 8). Patent
Owner’s declarant (i.e., Mr. Murphy) states that “Burst EDO” and “IBM’s
‘High Speed Toggle’” were attempts at creating “faster controllers and
memory devices without using the synchronous interface” but that they were
“unsuccessful” (Murphy Decl. ¶ 13). We are not persuaded by Patent
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Owner’s arguments or Patent Owner’s declarant’s (i.e., Mr. Murphy’s)
statements.
As an initial matter, neither Patent Owner nor Mr. Murphy appear to
provide sufficient evidence regarding specific costs, profits/losses, sales
figures, market share, etc. of either of the two products. Nor do either Patent
Owner or Mr. Murphy state specific parameters, criteria, or benchmarks that
may have been met (by the marketing or sales of the two products) – or not
met – to indicate a lack of commercial success of the two products. Without
more than a mere general statement that the products were “not
commercially successful,” Patent Owner does not adequately show that the
two products were, in fact, “not commercially successful.”
Even assuming that the two products were, in fact, “not commercially
successful,” Patent Owner and Mr. Murphy have not sufficiently
demonstrated a nexus between any alleged lack of commercial success of the
two products and any specific claim feature. Patent Owner argues that the
two products failed “to improve speed and efficiency of data transfer” (Req.
Reh’g 7), thus implying that the alleged lack of commercial success of the
two products was due to the alleged failure to improve speed and efficiency
of data transfer. In addition, Mr. Murphy states at paragraph 12 of the
Murphy Declaration that “[t]he inventions . . . have been very successful,”
that the inventors “solved the memory bottleneck problem,” that the
invention “[has] been instrumental in increasing DRAM system performance
to help meet the ever increasing demands of processors,” and that the
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invention “provide[s] for a robust memory system” (Murphy Declaration at
§ 12). However, Patent Owner and Mr. Murphy do not demonstrate
sufficiently that claim 1, for example, recites “improv[ing] speed and
efficiency of data transfer”, solving a “memory bottleneck problem,”
“increasing DRAM system performance to help meet the ever increasing
demands of processors,” or “a robust memory system,” for example.
Patent Owner argues that the combination of Baror and iRAM would
not have been obvious to one of ordinary skill in the art because “the
invention[] in the claims” was “met with initial skepticism” (Req. Reh’g 8,
citing Murphy Decl. 12-14). We are not persuaded by Patent Owner for at
least the reasons set forth in the Decision (Decision 8-9).
Mr. Murphy states that the invention of the ‘020 patent has been
“instrumental in increasing DRAM system performance” (Murphy Decl.
12), that “[o]thers have attempted to create faster controllers and memory
devices . . . but they were unsuccessful” (Murphy Decl. 13), that “many
experts . . . believed that DRAMs . . . should continue to use the simple
asynchronous interface” (Murphy Decl. 14), and that “such experts did not
believe that adding a synchronous interface that supported operation codes
. . . was beneficial or desirable” (id.). Mr. Murphy states that the experts
who “did not believe” were “proven wrong” (id.).
We are not persuaded by Mr. Murphy’s general statement that “many
experts” allegedly displayed “initial skepticism.” For example, Mr. Murphy
merely states that “many experts” were skeptical but does not further
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characterize the extent or context of the alleged skepticism. Indeed, “many
experts” may be skeptical (as opposed to “all experts” being skeptical),
while many “other” or “more” experts may not be skeptical. We note that
Mr. Murphy does not demonstrate or allege a particular proportion of
experts who were supposedly “skeptical” and whether the particular
proportion of allegedly skeptical experts would have been sufficient to
demonstrate that a relevant degree of skepticism (e.g., widespread
skepticism) existed. Indeed, based on Mr. Murphy’s statements, only an
insignificant degree of skepticism, if any, might have been present.
Patent Owner argues that “Rambus also presented evidence showing
praise for the inventors of the ‘5,020 patent” (Req. Reh’g. 8). In particular,
Patent Owner argues that “[t]he Board’s conclusion misses that the praise
was directed at Dr. Horowitz’s development of synchronous memory
interfaces, including the features recited in the claims of the ‘5,020 patent”
(Req. Reh’g 9). Patent Owner previously cited an article printed from http://
www.ieee.org/portal/pages/sscs/05Nov/Horowitz.html (Exhibit J) as
disclosing “praise” for the inventors.
Exhibit J discloses that Rambus, Inc. “used the technology pioneered
by Prof. Horowitz [i.e., research on high-speed, low power CMOS data link
interfaces for applications such as memory access in high-performance
computing and signal-processing systems] . . . to significantly increase the
bandwidth of the access to DRAM circuits” and “enabled an increase in the
rate at which a single memory chip can be accessed,” “Prof. Horowitz . . .
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continued research into increasing the performance of both serial and
parallel CMOS signaling and data transfer links,” that Prof. Horowitz
studied “input and output phase adjustment circuitry” and “where power is
actually consumed in various real microprocessors,” produced “key
architectural contributions to reduced instruction set computing,” was
involved in “the development of efficient timing models and parameter
extraction techniques for digital MOS circuits, and the pioneering of new
design techniques for CMOS and BiCMOS static random access memories.”
(Exh. J. at 2).
Hence, based on Exhibit J, Professor Horowitz allegedly performed
the following acts:
1) researched high-speed, low power CMOS data link
interfaces;
2) worked to increase the bandwidth of the access to DRAM
circuits;
3) worked to increase the rate at which a single memory chip
can be accessed;
4) researched potential methods of increasing the
performance of both serial and parallel CMOS signaling
and data transfer links;
5) studied input and output phase adjustment circuitry, and
6) produced “key architectural contributions” to reduced
instruction set computing.

We note that Exhibit J appears to merely list activities in which Prof.
Horowitz engaged but does not appear to specifically “praise” the activities.
Even assuming that at least some of the disclosure by Exhibit J constitute
“praise” of Prof. Horowitz, Patent Owner (and Exhibit J) fails to sufficiently
Appeal 2012-012567
Inter partes Reexamination Control No. 95/001,472
US Patent 6,715,020 B2

20
demonstrate a nexus between the alleged “praise” as specified in Exhibit J
and specific features of the claimed invention. For example, Patent Owner
(and Exhibit J) does not demonstrate persuasively that any of high-speed,
low power CMOS data link interfaces, increased bandwidth of access to
DRAM circuits, increased rate of accessing a single memory chip,
increasing performance of both serial and parallel CMOS signaling and data
transfer links, input and output phase adjustment circuitry, or specific “key
architectural contribution” to reduced instruction set computing are specific
claim features.
In the Rehearing Request, Patent Owner points out that the “praise” of
Exhibit J “was directed to increasing bandwidth on memory interfaces – i.e.,
‘high-bandwidth memory-interface technology’ – and resolving the memory
bottleneck problem” (Req. Reh’g 9). As previously discussed, however,
even assuming that Exhibit J discloses “praise” of “high-bandwidth
memory-interface technology” or “resolving the memory bottleneck
problem,” Patent Owner does not provide sufficient evidence demonstrating
a nexus between such praise and the claimed invention. For example, Patent
Owner does not sufficiently demonstrate or assert that claim 1, for example,
recites features that are alleged to be praised.
We have re-reviewed Patent Owner’s proffered evidence carefully and
thoroughly and have considered Patent Owner’s arguments but we are not
persuaded. We find no points that we have misapprehended or overlooked.
Therefore, the Request for Rehearing is DENIED.
Appeal 2012-012567
Inter partes Reexamination Control No. 95/001,472
US Patent 6,715,020 B2

21

DENIED

Patent Owner:

PAUL M. ANDERSON, PLLC
P.O. BOX 160006
AUSTIN, TX 78716

Third Party Requester

HAYNES AND BOONE, LLP
IP SECTION
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219

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